High-performance data acquisition signal chains used in industrial, instrumentation, and medical equipment require high dynamic range and accurate signal measurements while simultaneously addressing tough space constraints, thermal, and power design challenges. One of the ways to achieve a higher dynamic range is to oversample the converter to accurately monitor and measure both small and large input signals from the sensors.
Oversampling is a cost-effective process of sampling the input signal at a much higher rate than the Nyquist frequency to increase the signal-to-noise ratio (SNR) and resolution or effective number of bits (ENOB). As a general guideline, oversampling the ADC by a factor of four provides one additional bit of resolution, or a 6dB increase in dynamic range (DR). The DR improvement due to oversampling is defined by:
ΔDR = log2 (OSR) × 3dB
In many cases, oversampling is inherently implemented well in delta-sigma (Δ-Σ) ADCs with integrated digital filtering functionality, where the modulator clock rate is typically 32 to 256 times higher than the signal bandwidth. But oversampling is tougher to implement when fast switching between input channels is required.
SAR (successive approximation register) ADCs are also popular for the channel multiplexed based architecture that requires fast response to step input near full-scale (worst case) amplitude without any settling time issues. However, this puts an extra burden on the driver amplifier's requirements. To settle a kick-back coming from the switched capacitor DAC array of the SAR's input, an amplifier must have very good performance in terms of bandwidth, slew rate, and output drive capability. If it does not, non-linear effects will manifest in the output response.
The high throughput rate of a SAR ADC does allow oversampling. In this case, the low noise floor (achieved via a combination of low RMS noise and high throughput) with linearity is critical. Some of the high-performance SAR ADCs provide increased bandwidth, high accuracy, and discrete sampling in a small time window required for fast control and measurement applications. The fast throughput rate and low power with a small package size helps designers to meet space, thermal, power, and other key design challenges common to high-channel-density systems.
Although both ADC topologies can accurately measure signals extending down to DC, the SAR architecture usually allows the ADC core power to scale with the throughput rate. This minimizes the power consumption by at least 50 percent, which helps to meet the thermal constraints. In comparison, the Δ-Σ ADC typically has a fixed power draw. An example of high throughput together with power scaling can be found in ADI's 5MSPS 18-Bit AD7960 SAR ADC.
Oversampling with a SAR ADC can improve anti-aliasing and reduce noise. The low-pass filter that is placed in front of an ADC is there to minimize aliasing; but it also reduces noise by limiting bandwidth. The high oversampling ratio plus digital filter profile of the Δ-Σ ADCs minimize the anti-aliasing requirements at their analog inputs. Oversampling in the ADCs modulator reduces the overall noise.
SAR architecture without latency or pipeline delay enable fast control loops design. The SAR ADC such as AD7960 offers the lowest noise floor relative to the full-scale input floor, resulting in a higher SNR and excellent linearity performance. Even so, it cannot reject the 1/f noise close to DC (50/60Hz) content unlike Δ-Σ ADCs. There are a number of other ways to increase the dynamic range of an ADC such as adding ADCs in parallel and interleaving them in time. However, some designers may find this method to be cumbersome or impractical to implement for their system mainly due to the power, space, and cost reasons.
Have you designed with SAR and Δ-Σ ADCs? What problems did you have with them and how did you work around those problems?