I reread my last blog, LVDS Is Dead? Long Live LVDS & JESD204B, and realized that it raised the question: What is the driving force behind the migration to JESD204B?
I immediately jumped to the easy answer, i.e. how more bandwidth is desired across many segments of the market today, ergo JESD204B. The tougher answer to that question revolves, I believe, around interleaved ADC converters. When ADC converters are interleaved, two or more ADC converters with a defined clocking relationship are used to simultaneously sample an input signal and produce a combined output signal that results in a sampling bandwidth at some multiple of the individual ADC converters.
Interleaved ADC converters are definitely part of the push to a more efficient interface. Interleaved ADC converters offer several advantages to system designers. However, with the extra converter bandwidth comes a large amount of data that needs to be processed in an FPGA or ASIC. There has to be some efficient way to get all that data from the converter processed. It becomes impractical to continue using an LVDS interface in converters with sample rates in the gigasample range. So JESD204B is a nice, efficient way to get the large amount of data from the converter to an FPGA or ASIC.
Let's take a moment to step away from the interface though and look at interleaving for a moment. In communications infrastructure there is constantly a push for higher sample rate ADCs to allow for multi-band, multi-carrier radios in addition to wider bandwidth requirements for linearization techniques like DPD (digital predistortion). In military and aerospace, higher sample rate ADCs allow for multi-purpose systems that can be used for communications, electronic surveillance, and radar just to name a few. In industrial instrumentation, the need is always increasing for higher sample rate ADCs so that higher speed signals can be measured accurately. Let's begin this discussion by taking a look at the basics of interleaved ADCs.
Utilizing m number of ADCs allows for the effective sample rate to be increased by a factor of m. For the sake of simplicity and ease of understanding, let's just focus on the case of two ADCs. In this case, if two ADCs with each having a sample rate of fS are interleaved, the resultant sample rate is simply 2fS. These two ADCs must have a clock phase relationship in order to interleave them properly. The clock phase relationship is governed by equation 1, where n is the specific ADC and m is the total number of ADCs.
As an example, two ADCs each with a sample rate of 250MSPS are interleaved to achieve a sample rate of 500MSPS. In this case, equation 1 can be used to derive the clock phase relationship of the two ADCs and is given by equations 2 and 3.
Now that we know the clock phase relationship, the construction of samples can be examined. Figure 1 gives a visual representation of the clock phase relationship and the sample construction of two 250MSPS interleaved ADCs.
Two Interleaved 250MSPS ADCs Basic Diagram
Notice the 180° clock phase relationship and how the samples are interleaved. The input waveform is alternatively sampled by the two ADCs. In this case, the interleaving is implemented by using a 500MHz clock input that is divided by a factor of two. The divider takes care of sending the required phases of the clock to each ADC.
Another representation of this concept is illustrated in Figure 2.
Two Interleaved ADCs Clocking and Samples
By interleaving these two 250MSPS ADCs, the sample rate is increased to 500MSPS. This extends width of the converter's Nyquist zone from 125MHz to 250MHz, doubling the available bandwidth in which to operate. The increased operational bandwidth brings many advantages. Radio systems can increase the number of supported bands; radar systems can improve spatial resolution, and measurement equipment can achieve greater analog input bandwidth.