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Jonathan Harris

Interleaving Spurs: Gain Mismatches

Jonathan Harris
jonharris0
jonharris0
8/9/2013 2:19:48 PM
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Re: Frequency domain
Thanks for the great comments guys!

@Brad, thanks for the kind words.  I hope these blogs are provding some good insight for folks out there.

@Scott, thanks to you as well for the comment.  I think I see where you are going, but I would be concerned that adding or subtracting anything from the inputs would affect the integrity of the sampled signal.  I think in any calibration scheme we'd want to make sure we don't corrupt the sampled input signal.

@Michael, thanks to you too, for the comment and the link, what a well timed article!  Unfortunately, as you pointed out in the comments there, the details of the signal processing are missing.  It leaves the reader to wonder how the signal processing would affect their end system.  Is there some particular characteristic of the processing to be aware for certain types of signals?  Would there be any danger of signal corruption?  Also, I tend to see the type of mismatch discussed as more of a bandwidth mismatch than gain mismatch.  A mismatch in the bandwidth has gain and phase components that change over frequency.  It is all just semantics though...

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Michael Dunn
Michael Dunn
8/6/2013 9:12:14 PM
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Frequency domain
An article appeared recently on EDN.com about doing interleave correction in the frequency domain using the author's proprietary IP, instead of messing around trying to finesse gains, offsets, and presumably even timing offsets. Unfortunately, no implementation details were given:

http://www.edn.com/design/test-and-measurement/4418920/Wideband-error-correction-elevates-time-interleaved-ADCs

Any thoughts on this approach?

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Scott Elder
Scott Elder
8/6/2013 6:01:35 PM
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Couple of Thoughts on Gain Calibration
Jonathan,

1.  How about adding or subtracting a small percentage of voltage from the reference inputs?  I'm thinking one reference for the system and a gain factor (small, +/- 0.1% probably) into the ADCs?  This would require an offline calibration....but maybe not.  See (2).

2.  Perhaps one can make the assumption that since the ADCs are interleaved, the rms should be the same over some long period of time.  So one could, without going off line, continuously compute the RMS from each ADC and then adjust the reference as in (1).  Regulate the reference of one ADC to maintain constant RMS from both.

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B_Albing
B_Albing
7/30/2013 3:48:13 PM
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interleaving - now I get why it's tricky to do
Jonathan - good explanation. Now I get it. This all helps to explain why another company for whom I worked had some specialty software. They made it available to the customers buying the expensive very high speed and ultra high speed ADCs that customers planned on operating in interleaved mode.

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More Blogs from Jonathan Harris
We begin this series of blogs by taking a look at ADIsimADC, which is a quite relevant design tool for Jonathan Harris, an applications engineer in ADI's high-speed ADC group.
In this blog we’ll take this one step further and look at driving the ADC power supplies directly from a DC/DC converter.
Previously in this blog series we looked at using a DC/DC converter (switching regulator) in combination with an LDO to drive the power supply inputs to an ADC. What we found was that using the DC/DC converter to step down the input voltage for the LDO was a much more efficient way to drive the power supply inputs to an ADC.
We look at using a DC/DC converter along with an LDO to drive the ADC power supply inputs.
I thought it would be good to continue looking at the example I gave in my last blog where we looked using fewer LDOs and combining power supply rails on an ADC while maintaining isolation with ferrite beads.
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