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Jonathan Harris

Interleaving Spurs: Timing Mismatches

Jonathan Harris
jonharris0
jonharris0
8/29/2013 10:01:53 PM
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Re: Clock source
Actually a discussion on the different things that impact the ADC noise sounds like a good idea for a blog... :-)  I may take a slight detour and address that topic on a blog soon.

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jonharris0
jonharris0
8/29/2013 10:13:06 AM
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Re: Clock source
Razvan, this is a good question. Thanks for the comment. In order to obtain the true performance of the ADC, a low jitter clock source (~100fs) is needed.  As you mentioned, finding a clock source with this level of jitter is a little difficult.  You are also correct that a low jitter reference is usually required.  I am not aware of any modules that are out there that provide this low level of jitter.  Typically we use an input from the Rohde-Schwarz SMA100 signal generators to provide a low jitter (ala low phase noise) input.  Also, Wenzel makes some nice oscillators that have very low phase noise as well and can be used to clock high speed ADCs.  I'm not sure however if they offer anything that would be surface mount.  The ones that I use are powered from a 15V supply, have SMA connector outputs, and are about 2"x2" square.  Do also keep in mind that the overall SNR of the signal chain is also affected by the driver amplifier noise and gain as well as the AAF in front of the ADC.

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razvan.tataroiu
razvan.tataroiu
8/28/2013 3:53:32 PM
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Newbie
Clock source
Somewhat off-topic, but related to high-performance ADC timing: I'm seeing aperture jitter specifications for high-speed ADCs in the 100fs area. I understand that in order to obtain specified SNR performance, a clock source with similarly low jitter specs is needed. However I find it very difficult to obtain such a clock source as an integrated module. Although various PLL-based clock generator ICs exist with exceptionally low additive jitter (and, related to this post, adjustable delay for each clock channel), they still require a stable low-frequency reference. Could you perhaps recommend such a clock source available as a module from a well-known distributor? Or is it that I have to design a discrete solution?

Thank you for your insight.

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More Blogs from Jonathan Harris
I thought it would be good to continue looking at the example I gave in my last blog where we looked using fewer LDOs and combining power supply rails on an ADC while maintaining isolation with ferrite beads.
There are some disadvantages when driving low input supply voltages, where multiple LDOs may be required.
Keeping the power supply inputs on separate domains can minimize crosstalk and make it much harder for noise to interfere with ADC performance.
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After a good first two days and very enjoyable evenings of the IMS show, it was time for the last day, when traffic is typically good in the morning but tapers off as the day moves toward lunch and beyond.
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