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Jonathan Harris

Interleaving Spurs: Bandwidth Mismatches

Jonathan Harris
B_Albing
B_Albing
9/21/2013 7:55:20 PM
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Editor
Re: Re : Interleaving Spurs: Bandwidth Mismatches
@Per - any discussion of the higher Nyquist bands or zones is useful stuff. I may have to write a blog on this - unless you or Jonathan wants to.

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B_Albing
B_Albing
9/21/2013 7:50:57 PM
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Editor
Re: Re : Interleaving Spurs: Bandwidth Mismatches
@Per - thanks for the heads-up and the link to your article on our sister site.

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Per Lowenborg
Per Lowenborg
9/10/2013 3:08:06 AM
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Newbie
Re: Re : Interleaving Spurs: Bandwidth Mismatches
The right-hand part of Figure 5 shows the measured aliasing level in the system second Nyquist band, i.e. the third and fourth Nyquist band of the ADS5474 ADCs.

It is on the second page.

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jonharris0
jonharris0
9/9/2013 8:18:37 PM
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Blogger
Re: Re : Interleaving Spurs: Bandwidth Mismatches
I believe another poster had linked to your article in a previous comment.  It is definitely an interesting read.  A different way to approach the errors.  One limitation I noted as I re-read the article was that it was limited to within a Nyquist band.  Several customers I've had experience with cross Nyquist boundaries these days especially with multi-band applications becoming more popular.  Thanks for the comment!

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Per Lowenborg
Per Lowenborg
9/5/2013 8:06:41 AM
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Newbie
Re: Re : Interleaving Spurs: Bandwidth Mismatches
Thank you for this mismatch error walk-through.

If you are interested in seeing what digital mismatch error correction can achieve with bandwidth mismatch in terms of gain and phase-delay versus frequency, I can recommend to take a look at the following article I wrote recently for EDN T&M. You can find it at: 

http://www.edn.com/design/test-and-measurement/4418920/Wideband-error-correction-elevates-time-interleaved-ADCs

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jonharris0
jonharris0
9/3/2013 8:08:58 AM
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Blogger
Re: Re : Interleaving Spurs: Bandwidth Mismatches
Thanks for the great comments here all!  Indeed this is a mismatch that is quite difficult to handle.  My meaning was to make the circuit designs and the layouts as symmetric and matched as is possible to help minimize items that would affect the bandwidth of each channel.  This in my view is the most efficient way to combat bandwidth mismatch.  You'd need to pay careful attention first to the design to make sure each channel is designed as similar as possible, then make sure the layout is as matched as possible including not only the circuits but the routing as well.  The unfortunate things is that you still have process issues to battle as there are typically gradients across a wafer in terms of transistor beta and the like.  It still won't be perfect, but at least you know you've put your best foot forward.

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samicksha
samicksha
9/2/2013 3:25:15 AM
User Rank
Student
Re: Re : Interleaving Spurs: Bandwidth Mismatches
Interesting Blog@Jonathan: Diagrams and content of your blog keeps up the good clarity but i am little more curious on what really you denote as Good circuit design..is it you want perfect timing matches without any delay or mismatch..

The best way to minimize the bandwidth mismatch is to have very good circuit design and layout practices that work to minimize the bandwidth mismatches between the ADCs.

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Maciel
Maciel
8/31/2013 5:55:42 PM
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Newbie
Re: Re : Interleaving Spurs: Bandwidth Mismatches
In some situations this is not possible recourse but to use a uC, we solved this with greater ease because we have multiple AD channels available with a lower level of interference ...

But obviously this will depend on many factors, and especially the application.

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SunitaT0
SunitaT0
8/31/2013 2:31:56 PM
User Rank
Master
Re : Interleaving Spurs: Bandwidth Mismatches
The bandwidth mismatch is more problematic because it contains components from two other mismatched parameters like gain and frequency component. The greatest way to lessen bandwidth mismatch to get a very decent circuit design and layout exercises that work to lessen bandwidth mismatches between the interleaved ADC.

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