By now you may be wondering how many more mismatches we have to look at when dealing with interleaved ADCs... well, we've finally arrive at the last one, bandwidth mismatch.
So far we've examined offset, gain, and timing mismatch. Now we'll look at what perhaps can be considered the most difficult mismatch to combat, which is the bandwidth mismatch between interleaved ADCs. As shown in Figure 1, the bandwidth mismatch has a gain and a phase/frequency component. This makes bandwidth mismatch more difficult because it contains components from two of the other mismatch parameters, gain and timing mismatch.
Figure 1 Bandwidth Mismatch
In the bandwidth mismatch, however, we see different gain values at different frequencies. In addition, the bandwidth has a timing component, which causes signals at different frequencies to have different delays through each converter. The best way to minimize the bandwidth mismatch is to have very good circuit design and layout practices that work to minimize the bandwidth mismatches between the ADCs. The better matched each ADC is, the less the resulting spur will be.
Because of the variation in gain and timing over frequency, any type of algorithm to try and calibrate for the errors would be extremely complex. This would likely increase circuit and area overhead too much to make the benefits of the calibration worthwhile. As it turns out, proper layout techniques can help to minimize this mismatch while properly accounting for the other mismatches (offset, gain, and timing) makes a significant impact on the interleaving spurs.
On my last several blogs we've looked at the various mismatches that cause issues when interleaving ADCs. As we take a look back over this discussion it is apparent that many of the mismatches have something in common. Three of the four produce a spur in the output spectrum at fS/2 ± fin. The offset mismatch spur can be easily identified since it alone resides at fS/2 and can be compensated fairly easily. The gain, timing, and bandwidth mismatches all produce a spur at fS/2 ± fin in the output spectrum so the question is how to identify the contribution of each. Figure 2 gives a quick visual guide to the process of identifying the sources of the spurs from the different mismatches of interleaved ADCs.
Figure 2 Interrelated Nature of Interleaving Mismatches
The offset mismatch creates a spur that is isolated at fS/2. This is relatively simple to located and identify. If looking purely at gain mismatch alone, it is a low frequency, or DC, type of mismatch. The gain component of the bandwidth mismatch can be separated from the gain mismatch by performing a gain measurement at low frequency near DC and then performing gain measurements at higher frequencies. The gain mismatch is not a function of frequency like the gain component of the bandwidth mismatch.
A similar approach is used for the timing mismatch. A measurement is performed at low frequency near DC and then subsequent measurements are performed at higher frequencies to separate the timing component of bandwidth mismatch from the timing mismatch.
So that sums up our discussion on the various mismatches that we encounter when interleaving ADCs. I trust that the discussion has been useful and we all now know a bit more about interleaving ADCs. Stay tuned as we start taking a look at some ways that we might try to calibrate for these mismatches. There are several good papers out there that offer some interesting approaches. Again, keep those questions coming and we'll see where things take us.