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Jonathan Harris

Understanding JESD204B Link Parameters

Jonathan Harris
jonharris0
jonharris0
9/22/2013 9:07:20 PM
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Blogger
Re: JESD204B's application
Thanks Brad, perhaps another idea for future blog...

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B_Albing
B_Albing
9/22/2013 7:14:24 PM
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Editor
Re: JESD204B's application
@JH - thanks for providing a bit of addendum material regarding these different methods of outputing data streams.

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jonharris0
jonharris0
9/13/2013 3:36:21 PM
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Blogger
Re: JESD204B's application
These are all great comments and questions!  The progression of output technology in ADCs has gone from CMOS to LVDS as the mainstream technology today.  The JESD204 standard is emerging as the technology of choice for the output interface of ADCs.  In the wealth of ADC applications where sample rate is 250 MSPS and below, you see mainly LVDS.  Some ADCs up to the GSPS range still use LVDS but it gets very ugly in terms of number of I/O and routing.  The real advantage for JESD204 (especially JESD204B) comes from ADCs with sample rates that go above 500 MSPS and into the GSPS range.  It allows the data to be output on much fewer outputs than that required for LVDS.  The trend is looking eerily similar to what happened when things transitioned from CMOS to LVDS.  It is all about speed and the higher sample rate converters need a faster, more efficient interface.  I have a recent article in the Xilinx Xcell journal that discuss some of this.  It is at: http://issuu.com/xcelljournal/docs/xcell_journal_issue_84/48?mode=window&viewMode=doublePage

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samicksha
samicksha
9/13/2013 3:33:24 AM
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Student
Re: JESD204B's application
@Daej: That is where JESD204B helps us in overcoming the limitations possesed like CMOS or LVDS, such as synchronization across multiple channels or board design complexity.

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DaeJ
DaeJ
9/11/2013 9:26:14 PM
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Master
Re: JESD204B's application
Any application requiring any high speed data transfer such as wireless communication in the automotive industry might require JESD204B. But, when module is integrated to other modules such as EMS and BCM, data transfer rate might be mismatched in the gateway between subsystem. Integration implementation should be carefully reviewed in the vehicle architecture.

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samicksha
samicksha
9/11/2013 5:14:15 AM
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Student
Re: JESD204B's application
I guess this help addressing cost constraints of a range of high speed ADC applications such as LTE.

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eafpres1
eafpres1
9/11/2013 12:32:33 AM
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Blogger
Re: JESD204B's application
I'm wondering a similar question to DaeJ: I have noted that LVDS is used in automotive (which typically is slow to adopt technologies).  Do you think automtove applications will pursue JESD204B devices?

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DaeJ
DaeJ
9/10/2013 7:17:37 PM
User Rank
Master
JESD204B's application
I am wondering what type application need to use this type protocol in detail. It might require more than 10GHz frequency band. For example, Video based system might require the fast data transmission to avoid the picture resolution distortion.

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More Blogs from Jonathan Harris
In Part 1, our blogger looked at how many clocking products specify the phase noise of the device but don't specify jitter. In the second part, he offers a real-life example.
Many clocking products specify the phase noise of the device but don't specify jitter. Let's take a look at how we can go from phase noise to jitter.
One of the most critical areas on an ADC that can affect performance is clock noise. Good layout and routing techniques coupled with an optional filter can do wonders in improving key specs.
There are many ways in which noise can enter an ADC or signal distortion can occur. We look at some of these, including aliasing.
This time, let's look at the noise that can enter the ADC through its signal and common mode inputs. Then we'll go through a noise calculation to see how it's done.
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