So now we've had a chance to take a look at the many mismatches that exist when we time-interleave ADCs. As I looked over my previous blogs and comments (check related posts below) it became apparent that I hadn't given an idea yet of how big the spurs are as a result of the mismatches. By now we know that these various mismatches cause interleaving spurs, and we know where they are, but how do we know how big they are?

Let's now put on our mathematician's hat for just a moment… I know, I know, we don't like to wear this hat too long as an engineer -- we want to be doing the fun engineering stuff. Alas, at times we must play the part of the mathematician.

Just as we did with the progression of looking at the types of mismatches, let's first begin with the offset mismatch spur. As you may recall, the offset mismatch between the two ADCs will produce a spur at f_{s}/2. So how do we know how big this spur is going to be? Let's take a look at equation 1 below where *OffsetMismatch* is given in number of codes.

**Equation 1**

Now, let's consider we have a typical offset mismatch between two 14-bit ADCs in a dual channel device. Typically this is about one-half percent of full scale for the nominal value. This means that the number of codes would be one-half percent of 2^{14} = 81.92 codes. Substituting this in equation 1 we get the following:

Well, that is an interesting result! One-half percent of full scale doesn't seem like much of an error, but it results in a fairly large offset spur. Most applications today for high-speed ADCs cannot tolerate this type of spur. This would dominate the spurious free dynamic range (SFDR) specification for the interleaved ADCs. Most applications require an SFDR of at least 70dBc or better, which means this is much too high. Let's take a look at where we need to be in order to meet or exceed a 70dBc (-71dBFS) level. Figure 1 below gives us a plot of the offset spur level versus the offset mismatch in percent full scale.

**Figure 1**

Offset Spur vs. Offset Mismatch (Interleaved 14-bit ADCs)

This gives us quite an interesting picture. In order to meet typical spurious requirements of 70dBc (-71dBFS), the offset mismatch must be less than 0.025 percent of full scale for a 14-bit converter. This gives us an idea of how closely the offset needs to be matched. That is pretty small! We'd better have the offsets matched pretty well. Stay tuned as next time we'll take a look at the math for the gain offset. We'll see how much gain mismatch translates into the interleaving spur at f_{s}/2 ±f_{in}.

**Related posts:**