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Jonathan Harris

Interleaving Spurs: More Math Details for Gain Mismatch

Jonathan Harris
jonharris0
jonharris0
6/19/2014 10:24:00 AM
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Slight correction
In the equation above for the interleaving spur for the gain, inside the log formula should be [(1- 1.98/2)/2].  Apologies for the error.  Thanks to a coworker for pointing this out.

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SunitaT0
SunitaT0
10/29/2013 3:13:51 AM
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Re : Interleaving Spurs: More Math Details for Gain Mismatch
Spurious performance and Achievable resolution of ADCs are strongly connected to the supreme sampling occurrence of the device. Nowadays, in mid-2013, sample rates of commercially available 16-bit massive, single-core (non-added) ADCs are restricted to 250 MS/s though 14-bit ADCs could be found up to 400 MS/s.

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