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Jonathan Harris

Interleaving Spurs: More Math Details for Gain Mismatch

Jonathan Harris
jonharris0
jonharris0
6/19/2014 10:24:00 AM
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Slight correction
In the equation above for the interleaving spur for the gain, inside the log formula should be [(1- 1.98/2)/2].  Apologies for the error.  Thanks to a coworker for pointing this out.

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SunitaT0
SunitaT0
10/29/2013 3:13:51 AM
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Re : Interleaving Spurs: More Math Details for Gain Mismatch
Spurious performance and Achievable resolution of ADCs are strongly connected to the supreme sampling occurrence of the device. Nowadays, in mid-2013, sample rates of commercially available 16-bit massive, single-core (non-added) ADCs are restricted to 250 MS/s though 14-bit ADCs could be found up to 400 MS/s.

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More Blogs from Jonathan Harris
After looking at the performance metrics in the online ADC simulator tool it is a great time to look at another online ADC tool called the Frequency Folding Tool. It is a useful simulator that helps to understand the effects of aliasing in an ADC.
. I received a very good reader question from my last blog post regarding the various parameters that are reported by the tool. Letís take a look at an example and explore the parameters that are returned. In this example we will look at the AD9643-250.
Now letís look at the web-based evaluation tool. This does not require downloaded software to run as it is purely ran from the web
First, to make any ADC operate we need to set up the input stimuli.
We begin this series of blogs by taking a look at ADIsimADC, which is a quite relevant design tool for Jonathan Harris, an applications engineer in ADI's high-speed ADC group.
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