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Jonathan Harris

Interleaving Spurs: More Math Details for Gain Mismatch

Jonathan Harris
HarrisUser
HarrisUser
3/2/2017 9:33:49 PM
User Rank
Newbie
Re: Slight correction
I don't think your coworker is quite correct. They are likely objecting the negative arguement of the log. If you use ABS of the log arguement, then the prose defining the full scale voltages and the equation symbology match. Otherwise I believe you need to specify that the lower fullscale voltage is used as VFS1 and the larger as VFS2 - which is the opposite of what the prose states. And the value is numerically what you show.

What bothers me is that if I set say VFS1 to 1.8 and VFS2 to 2, using your equation, and then reverse the roles letting VFS1 be 2 and VF2 be 1.8  then even using the ABS function doesn't help as the values are ~ 1 dB different. Which bothers me that the dBc would be different depending on which converter I label as 1 or 2. So I am guessing that your comment about log arguement relates the defnition in the equation and that VFS1 is to be the lower fullscale voltage and VFS2 is to be the larger FS voltage. Regardless of which converter might be labels "1" or "2" say on a drawing.

So can you explain the proper interpretation or conditions for deriving the formula given so that the equation can be properly applied.

 

THanks..

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jonharris0
jonharris0
6/19/2014 10:24:00 AM
User Rank
Blogger
Slight correction
In the equation above for the interleaving spur for the gain, inside the log formula should be [(1- 1.98/2)/2].  Apologies for the error.  Thanks to a coworker for pointing this out.

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SunitaT0
SunitaT0
10/29/2013 3:13:51 AM
User Rank
Master
Re : Interleaving Spurs: More Math Details for Gain Mismatch
Spurious performance and Achievable resolution of ADCs are strongly connected to the supreme sampling occurrence of the device. Nowadays, in mid-2013, sample rates of commercially available 16-bit massive, single-core (non-added) ADCs are restricted to 250 MS/s though 14-bit ADCs could be found up to 400 MS/s.

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