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Jonathan Harris

Interleaving Spurs: More Math Details for Gain Mismatch

Jonathan Harris
jonharris0
jonharris0
6/19/2014 10:24:00 AM
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Slight correction
In the equation above for the interleaving spur for the gain, inside the log formula should be [(1- 1.98/2)/2].  Apologies for the error.  Thanks to a coworker for pointing this out.

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SunitaT0
SunitaT0
10/29/2013 3:13:51 AM
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Re : Interleaving Spurs: More Math Details for Gain Mismatch
Spurious performance and Achievable resolution of ADCs are strongly connected to the supreme sampling occurrence of the device. Nowadays, in mid-2013, sample rates of commercially available 16-bit massive, single-core (non-added) ADCs are restricted to 250 MS/s though 14-bit ADCs could be found up to 400 MS/s.

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More Blogs from Jonathan Harris
In this installment I’d like to revisit the example that was covered in my January blog post
We will continue looking at the AD9680 as an example just as we did in part 1. Similar to the real mode operation of the DDC the normalized decimation filter responses are the same regardless of speed grade.
Let’s now take a closer look at the decimation filtering and how ADC aliasing influences the effective response of the decimation filtering
Increase the decimation ratio in the DDC to see the effects of frequency folding and translating when a higher decimation rate is employed along with frequency tuning with the NCO.
Let’s now take a look at a real example with the AD9680-500. We’ll see how this simple yet powerful tool can be used to aid in understanding the aliasing effects of an ADC as well as help with understanding effects of some digital processing blocks in the AD9680.
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