datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com   UBM Tech
UBM Tech
Home    Bloggers    Blogs    Article Archives    Messages    About Us   
Tw  |  Fb  |  In  |  Rss
Jonathan Harris

Interleaving Spurs: The Mathmatics of Timing Mismatch

Jonathan Harris
jonharris0
jonharris0
10/28/2013 8:44:27 AM
User Rank
Blogger
Re: Re : Interleaving Spurs: The Mathmatics of Timing Mismatch
Thanks for the comments yalanand.  You are correct, probably the simplest interleaving mismatch to look at is the offset mismatch.  I've discussed that here http://www.planetanalog.com/author.asp?section_id=3041&doc_id=560484 and here http://www.planetanalog.com/author.asp?section_id=3041&doc_id=561191

Definitely appreciate all these comments from everyone, please keep them coming! :-)

50%
50%
yalanand
yalanand
10/27/2013 7:14:26 AM
User Rank
Newbie
Re : Interleaving Spurs: The Mathmatics of Timing Mismatch
Probably the calmest of these to realize is the offset disparity between the two ADCs.  Each ADC would have a related DC offset value. When the two ADCs are enclosed and samples are learned alternatively back and forth among the two ADCs, the DC offset of each consecutive sample is altering. 

50%
50%
jonharris0
jonharris0
10/18/2013 8:20:35 AM
User Rank
Blogger
Re: Timing
Hi Sunita, thanks for the comment. You are correct, typically SFDR is defined by the fundamenatl and the most prominent harmonic. In the case of the interleaved ADC, with enough mismatch, the interleaving spur can be significantly higher than the highest harmonic.  In this case, it drives what the actual SFDR is since the dynamic range is then typically limited by the amplitude of the interleaving spur.

50%
50%
samicksha
samicksha
10/10/2013 6:22:57 AM
User Rank
Student
Timing
Mathematics has always been a nightmare for, but if we refer SFDR it is between the amplitude of the frequency being generated and the amplitude of the most prominent harmonic.

50%
50%
More Blogs from Jonathan Harris
As an engineer it is always rewarding when one can calculate an expected result and see the measurement in the lab line up with that calculation.
In Part 1, our blogger looked at how many clocking products specify the phase noise of the device but don't specify jitter. In the second part, he offers a real-life example.
Many clocking products specify the phase noise of the device but don't specify jitter. Let's take a look at how we can go from phase noise to jitter.
One of the most critical areas on an ADC that can affect performance is clock noise. Good layout and routing techniques coupled with an optional filter can do wonders in improving key specs.
There are many ways in which noise can enter an ADC or signal distortion can occur. We look at some of these, including aliasing.
flash poll
educational resources
 
follow Planet Analog on Twitter
Planet Analog Twitter Feed
like us on facebook
our partners
Planet Analog
About Us     Contact Us     Help     Register     Twitter     Facebook     RSS