We've used our nifty mathematician's hat to look at the magnitude of spurs from the offset and gain mismatches, so now let's use it to quantify the spur level due to the timing mismatch. As we've seen in our previous discussions, the spur due to the timing mismatch appears at f_{S}/2 ± f_{in}, which is the same location that the gain mismatch spur appears.

The outcome of our discussion will now leave us with information that will tell us how much of the spur at f_{S}/2 ± f_{in} results from the gain mismatch and how much results from the timing mismatch. This is important since it will help us when interleaving to be able to tell which mismatch is causing us the most trouble. Let's hope that we don't end up in a position where both are really bad... but that isn't the point when trying to interleave in the first place. We want to start at the beginning of the design process with trying to minimize the mismatches.

So let's dive into that math once again by putting on our mathematician's hat and take a look at how we calculate the magnitude of the spur at f_{S}/2 ± f_{in} due to the timing mismatch. I think we are close to putting that hat away for a while and getting our engineer's hat back on, but let's use this math hat just a little longer.

Let's look at the calculations now and see how big the spur from the timing mismatch is going to be. Let's take a look at equation 1 below where ω_{A} is the analog input frequency and Δτ_{E} is the timing mismatch.

Now, let's consider we have a typical timing mismatch between two 14-bit 250MSPS ADCs in a dual channel device. A typical value might be around 1ps. Substituting this in equation 1 we get the following:

Well, at least this result is a little more encouraging than what we first looked at with the gain mismatch! A 1ps timing mismatch will result in an interleaving spur of 70dBc at f_{S}/2 ± f_{in}. That's right on the mark for about the maximum spur level most applications can tolerate. This would still easily dominate the spurious free dynamic range (SFDR) specification for the interleaved ADCs.

The 2^{nd} and 3^{rd} harmonics and any other spurious output would most likely be less than 70dBc. Let's take a look now at what we can do to exceed a 70dBc level. We'd like to get it lower since there are applications out there that need a spurious free dynamic range of 80 to 90dBc. Below in Figure 1 the magnitude of the timing mismatch spur is shown with respect to the timing mismatch given in picoseconds.

**Figure 1**

Timing Spur vs. Timing Mismatch (Interleaved 14-bit ADCs).

This plot shows us a couple of things. Similar to the gain mismatch plot, the magnitude of the spur roughly follows an exponential decay where, once the mismatch approaches 10ps, the plot of the spur magnitude is becoming nearly flat. Also, it tells us that we need to get the timing mismatch really small (femtoseconds range) in order to get the spur magnitude into the 90dBc range. This gives us an idea of how closely the timing between the two ADCs needs to be matched. When we talk femtoseconds that is pretty small!

However, as process technologies shrink and matching techniques improve, it becomes somewhat easier to minimize the mismatch in timing between the interleaved ADCs. Note that layout is only one piece of the puzzle. At the high speeds ADCs are reaching today, up into the gigasample range, there needs to be some sort of calibration in place to enable reducing the timing mismatch into the femtosecond range. This tells us that there is hope; we just need to figure out a good calibration scheme to reduce the mismatch. Hopefully we'll be able to take a high level look at some proposed schemes soon, unless your comments and questions take us on a different path.

So this mathematician's hat came in handy. Occasionally, we engineers need to put it on so we can understand the issues we face in our engineering world. Luckily we can put it down again and have some engineering fun. Keep treading and keep those comments and questions coming.

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