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Jonathan Harris

ADC Noise: A Second Look, Part 2

Jonathan Harris
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jonharris0
jonharris0
12/12/2013 10:20:58 AM
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Re: Ground and Power planes
I would clarify just one point here.  The return currents in a system will find the path of least inductance back to the source.  This is important to remember in high frequency designs.  In very low frequency designs, it is the path of least resistance but as we move up in frequency the return paths are defined by where the current finds its least inductive path.  There are many good EM simulators out there to help show these return paths.

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jonharris0
jonharris0
12/12/2013 10:16:16 AM
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Re: Re : ADC Noise: A Second Look, Part 2
@yalanand, I don't think I've seen any evidence that suggests the number of outputs bits has an adverse impact on system noise.  Are you inferring that an increase in the number of LVDS lines might cause this?  I would suspect this to be the case.  The potential is increased for noise coupling onto the data lines since there are more output bits, but since most converters are LVDS today (and moving to JESD204B) the differential nature of the signals makes them more immune to noise.  In addition, on converters with JESD204B there is a scrambling option that can be enabled (providing both the ADC and FPGA support it) that would help with any EMI that may be produced by the data lines.  Hope this helps!

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yalanand
yalanand
11/30/2013 2:18:32 PM
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Re : ADC Noise: A Second Look, Part 2
@Jonathan, Thanks for the post. I want to know, if the number of  output  of bits  of analog to digital converter are increased ,how it will effect on the noise of the system and are there any advanced techniques to remove noise like this?

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DaeJ
DaeJ
11/18/2013 5:29:41 PM
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Re: Ground noise
The goal is of ADC is to get the correct digital value in corresponding analog data as removing noise and delay. As one of factors, the delay could be minimized as updating decoding process inside ADC.

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amrutah
amrutah
11/18/2013 3:59:16 PM
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Re: Ground noise
@DaeJ:

 "There are a delay (latency) between the time a signal is sampled and the time the digital output is generated in ADC. This delay causes the error of the presented data value..."

   This delay would be present for all the samples of the input ADC signal, why do you say that this will case error instead of time-shifted digital output.

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jonharris0
jonharris0
11/18/2013 9:17:42 AM
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Thanks for the comments
Very good points here by all.  Thanks for the many great comments.  I hope to start looking at these concepts as we talk about all the noise entry points in my upcoming blogs.

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DaeJ
DaeJ
11/17/2013 2:47:03 PM
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Re: Ground noise
Delay and Noise

There are a delay (latency) between the time a signal is sampled and the time the digital output is generated in ADC. This delay causes the error of the presented data value. This latency would be critical factor in the high speed communication application. If amplifier is used in the signal condition of ADC, this improves signal paths, but increases noise which means noise would be increased with signal level. Therefore engineer might consider ways to design the circuit with board in order to achieve the minimization of noise.   

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Netcrawl
Netcrawl
11/16/2013 10:39:32 PM
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Re: Ground and Power planes
The ground and power planes are key factors in reducing noise voltage, proper design and good layout make this possible, we starting project we need to take a closer look at this matter, the ground is our reference point. 

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DaeJ
DaeJ
11/15/2013 10:06:59 PM
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Re: Ground and Power planes
The method to use interior layers to route signal would reduce noise using through-hole and Blind/Buried vias unless cost and size is issue in the view point of power distribution. PCB material would contribute to noise reduction.

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amrutah
amrutah
11/15/2013 5:50:34 PM
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Ground and Power planes
"It is imperative to consider all the current return paths in the design rather than to assume the ground is a stable reference point."

   This is exactly the point that needs to be thought off.  The ground and Power plans have to be least resistive so that the rsulting noise voltage is as minimum as possible.  The ground network even though star connected or whatever network should have a low resistive current path.

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More Blogs from Jonathan Harris
We look at using a DC/DC converter along with an LDO to drive the ADC power supply inputs.
I thought it would be good to continue looking at the example I gave in my last blog where we looked using fewer LDOs and combining power supply rails on an ADC while maintaining isolation with ferrite beads.
There are some disadvantages when driving low input supply voltages, where multiple LDOs may be required.
Keeping the power supply inputs on separate domains can minimize crosstalk and make it much harder for noise to interfere with ADC performance.
As is typically the case, at least from my observance in the last four years, the second day of the show proved to be the busiest.
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