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Jonathan Harris

ADC Noise: How the Clock Input Can Help

Jonathan Harris
jonharris0
jonharris0
1/27/2014 8:30:26 AM
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Re: Phase noise and Jitter
Hi amrutah, these are all great points and questions.  Indeed the clock is often overlooked when it shouldn't be.  Definitely one of the biggest contributors to noise in an ADC is the phase noise of the input clock source.  Other factors may not be as big but should not be overlooked.  The noise impact will be less from what is picked up via a poor layout than from a clock source with poor phase noise or poor spurious even.  I think you'll enjoy my next post.  I'll be looking at close in vs wideband phase noise and how they affect the ADC in different ways.  Thanks for the great comments and questions!

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amrutah
amrutah
1/25/2014 1:57:48 PM
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Phase noise and Jitter
Jonathan,

   I will be eagerly waiting for your next blog post.  How the low and high frequency components phase noise affect the ADC noise.  Different jitter that affect the ADC noise, meaning contributions of peak litter, period jitter or total accumulated jitter.

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amrutah
amrutah
1/25/2014 1:49:27 PM
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CLOCK phase noise/Jitter
Jonathan,

   I think the contribution of phase noise/jitter of the clock source is the main contributor to ADC Noise compared to the noise that the clock picks on the way to ADC. How substantial can the noise contribution be compared to the jitter?

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amrutah
amrutah
1/25/2014 1:08:27 PM
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Master
Clock input

Yes, I agree that the clock input source can be one source of noise and usually is considered at last moment. As you mentioned modelling it as a mixer should give a good analysis upfront when dealing with the noise analysis and specification limit.

   Usually the high speed clock source will be a PLL/DLL system which cannot be placed close to the ADC, and as such having a filter makes it more viable solution.  But that increases the BOM or onchip area

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More Blogs from Jonathan Harris
We will continue looking at the AD9680 as an example just as we did in part 1. Similar to the real mode operation of the DDC the normalized decimation filter responses are the same regardless of speed grade.
Let’s now take a closer look at the decimation filtering and how ADC aliasing influences the effective response of the decimation filtering
Increase the decimation ratio in the DDC to see the effects of frequency folding and translating when a higher decimation rate is employed along with frequency tuning with the NCO.
Let’s now take a look at a real example with the AD9680-500. We’ll see how this simple yet powerful tool can be used to aid in understanding the aliasing effects of an ADC as well as help with understanding effects of some digital processing blocks in the AD9680.
Back in my April blog post this year, we took some time to look at the Frequency Folding Tool that is available on the Analog Devices web site. I would like to revisit this tool as there have been a few handy improvements that have been made based on some great feedback.
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