It has been an interesting journey so far, looking at the sources of potential noise in an ADC. We've looked at the analog and digital power supply inputs and the ground connection. Along those lines, we also took a look at PSRR and PSMR. After that I discussed noise involving the analog inputs of the ADC. Now, let's take a look at one of the most critical places on an ADC to pay attention to noise -- the ADC clock input.
Any noise that enters the ADC through the clock circuitry can directly make its way to the output. The noise mechanism involving this circuit in the ADC can be thought of as a mixer. Thinking of this input in this manner when looking at noise really puts things into perspective. Noise frequencies that enter the ADC through the clock input will get mixed onto the analog input signal and show up in the FFT at the output of the converter.
There are a couple of things to be aware of relating to the clock circuit and the associated physical layout. First, it is good practice to keep the clock driver placed close to the ADC to keep the routing as short as possible. The less distance the clock signal travels the less likely it is to pick up any errant noise that may exist in the system. Even though most ADC clocks are differential, and offer resistance to common mode noise, there isn't complete noise immunity. One option is to add a band pass filter with a center frequency at the clock frequency of the ADC, as in the figure below.
Figure 1. Typical ADC LVDS clock circuit (filter optional).
This filter should be placed close to the ADC in order to remove any noise that may have coupled onto the clock signal in the system. It is better to place the filter closer to the ADC, since placing the filter closer to the clock driver allows noise to couple onto the clock signal after the filter and make its way into the ADC.
Not only is it important to pay attention to the placement and routing of the clock driver and ADC, but it is also important to consider the clock driver itself. Utilizing good layout and routing techniques and optionally filtering the clock signal help to reduce external sources of noise, but don’t forget to consider the clock source itself. It is important to choose a clock driver that has low phase noise. However, you can also focus on jitter depending on your preference.
One of the common issues I see when working with customers is that a good clock source is not chosen to drive the ADC. The result is typically poor SNR performance from the ADC. It is very much like the old saying: "If you put garbage in, you will get garbage out."
In my next blog, we’ll move on to discussing the impacts of phase noise on the noise performance (SNR) of the ADC. We will look at how to calculate the impact phase noise of the clock driver on the SNR of the ADC. Stay tuned as we continue to look at noise in an ADC. I hope you are having fun as we go along. In the meantime, please keep the questions and comments coming on our message boards.