In part 1 of this series, we took a look at the equations and the math we will need to calculate the jitter based on the phase noise of a clock source. Now let’s take that math and put it to some good use on a real-world scenario.

In this example we will look at clocking the AD9643 dual channel 14-bit 250 MSPS ADC with the AD9523 low-jitter clock generator. A common clock frequency utilizing these particular products is 245.76 MHz, so we will use a 30.72 MHz reference (external oscillator) for the AD9523 and set up the internal registers to generate a low-jitter clock output for the AD9643. Let’s now recall the jitter equations we looked at last time:

Recall that I mentioned that we could use an approximation to predict the SNR impact from the jitter of the clock source. I mentioned that it is the wideband phase noise that's the most significant. We can use the wideband phase noise of the AD9523 from a 10 MHz offset out to the encode bandwidth (245.76 MHz) to predict the SNR of the ADC as illustrated in Figure 1.

Figure 1. Phase Noise Approximation Over the Encode Bandwidth

From the AD9523 I have copied in the phase noise plots that were generated under two conditions. The first is with an output clock frequency of 122.88 MHz and the second is with an output clock frequency of 184.32 MHz. Now I will make another approximation, albeit one that is a bit looser in terms. I will use the data in these two plots and perform a linear interpolation to approximate what the phase noise will be at 10 MHz offset with an output clock frequency of 245.76 MHz.

Figure 2. AD9523 Phase Noise, fCLOCK = 122.88 MHz

Figure 3. AD9523 Phase Noise, fCLOCK = 184.32 MHz

With an output frequency of 122.88 MHz, the phase noise is -158.3307 dBc/Hz at a 10 MHz offset. Similarly, with an output frequency of 184.32 MHz, the phase noise is -156.2706 dBc/Hz. Performing a linear interpolation, the expected phase noise at a 10 MHz offset with an output frequency of 245.76 MHz is -154.21 dBc/Hz (as shown in Figure 1). Now we’ll use our equations for the area approximation to get the integrated phase noise.

Now we have all the pieces we need, but we are lacking just one final equation. We need to calculate the impact from this jitter on the SNR of the AD9643. Let’s now see what that equation looks like and plug in what we know. We know the clock frequency and the rms jitter. From the AD9643 datasheet we have an SNR value of 71.4 dBFS at 140 MHz analog input frequency. Let’s use the equation and see what the results are:

So now we have an expected SNR value of 68.763 dBFS when clocking the AD9643 with the AD9523. The final check is to actually set this up in the lab and check our numbers. Let’s take a look at Figure 4 and see how we did with our calculations.

Figure 4. AD9523 Clocking AD9643 at 245.76 MHz with fIN = 140.1 MHz

The lab results show an SNR value of 68.848 dBFS: This is quite a nice result! This tells us that I was probably a bit pessimistic with the expected phase noise of the AD9523, but the actual measured result is quite close to the predicted value of 68.653 dBFS. Once again, it is great to see such nice agreement between the predicted and measured results.

Stay tuned as we continue to look at noise and the impacts on the performance of an ADC. Thanks for the great questions that many of you readers are asking! I’ll be looking to dive into more detail to answer some of these as we continue looking at ADC noise.