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Jonathan Harris

ADC Noise: The Clock Input & Phase Noise, Part 3 – Test Setup

Jonathan Harris
jonharris0
jonharris0
4/29/2014 8:02:29 PM
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Blogger
Re: Two PCB –Phase/Clock Noise
Hi DaeJ, the AD9523 phase noise will defintely be affected by the jitter of its reference source.  The point here in this blog was not to evaluate the AD9523 jitter performance but rather to look at the effect of the output jitter (phase noise) on the SNR of the AD9643.  Also, you have a very good point with the PCB.  It is always important to consider good design practices when designing PCBs such that additional noise from other sources on the PCB do not impact the noise in the ADC.  I'd recommend looking back over some of my blogs related to ADC noise for some nuggets along those lines.  Thanks for the great comments!

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DaeJ
DaeJ
4/19/2014 6:50:52 PM
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Master
Two PCB –Phase/Clock Noise
Firstly, it would be better to review other components with AD9523 in order to understand how SNR is affected in the test setup. Secondly, engineer might investigate Phase and Clock noise in different layer design of PCB board. For example, figure 2 shows that the number of input source is feeding into one of PCB, influencing the noise naturally.

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More Blogs from Jonathan Harris
. I received a very good reader question from my last blog post regarding the various parameters that are reported by the tool. Let’s take a look at an example and explore the parameters that are returned. In this example we will look at the AD9643-250.
Now let’s look at the web-based evaluation tool. This does not require downloaded software to run as it is purely ran from the web
First, to make any ADC operate we need to set up the input stimuli.
We begin this series of blogs by taking a look at ADIsimADC, which is a quite relevant design tool for Jonathan Harris, an applications engineer in ADI's high-speed ADC group.
In this blog we’ll take this one step further and look at driving the ADC power supplies directly from a DC/DC converter.
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