In the first article of this series, Build Your Own Curve Tracer, Part 1: Introduction, two-port analyzers (TPAs) in general and the TPA presented here, the TPA202, were described. Part 2 of this series starts with a summary of the TPA202 circuit description. It is derived from the TPA202 Manual which is open-source and available from data sheet. It contains the more detailed circuit explanation.
The TPA202 decomposes into four functional subsystems: the input-port and output-port source-measure units (SMUs), the DVM, and the power supply. We start with the input-port SMU.
Input-Port SMU, Switch Scaling and Selection
First, the all-important circuit diagram is shown below. The +12 V supplies are actually closer to 13 V.
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The TPA202 input-port SMU consists of an amplifier followed by a high-side ISN. One of the avoided complications of a non-
C design is that the front-panel controls are inherently isolated and do not require additional translator circuitry, isolation circuits, or power supplies. The INP input from pot R1 has a range of the ±12 V supplies. (The pot value is not critical; a 10 kΩ pot will do as well.) The pot wiper voltage range is reduced by the R30, R31 divider to that of the input drive (IDR) amplifier input range of ±1 V. The S1 switch selects whether the input source is a voltage (V) or current (I) source based on which feedback path is selected.
U25A is the first stage of a larger noninverting op-amp with a voltage gain set by R78 and R96 to 10. Op-amp U25A has insufficient output current to meet the ±100 mA spec. The additional output stage is a discrete BJT Darlington common-collector amplifier. Q34, Q35 and sense resistors R80, R83 provide overcurrent protection and limit output current to a value somewhat above ±100 mA.
The current-sense circuit (IISN) is the two-op-amp differential amplifier, U26. It inputs the voltage developed across range-switched sense resistors R32 - R37, R40, R41 that span 7 decades of current, from 100 nA fs to 100 mA fs. At the full-scale range values, they drop 0.1 V. The diff-amp has a gain of 10 for an IISN output of ±1 V, which spans the DVM input range. The diff-amp inputs are those of JFET-input op-amps which are high in resistance and conduct negligible current. However, the sense-resistor voltage drop - the sense voltage, νS - causes the port output voltage at IDR+ to be up to 0.1 V less than the amplifier output voltage at IVDR-ISN. Consequently, the port output voltage of ±10 V fs is sensed by U25B and divided by 10 by R72, R73 and R74 to become IVSN with the DVM input range of ±1 V. R72 is adjusted in calibration for the correct division ratio.
Because IVDR has a range of ±10 V and this is within the common-mode linear input range of the op-amps operating from the ±12 V supplies, and because the 2P7T range switch as an analog front-panel component is isolated and electromechanical, a high-side IISN (ISN-H) is an optimal choice because it allows the input SMU to operate from grounded supplies and have a grounded output. (IDR– = COM = ground)
The disadvantage of a high-side ISN is that it floats over the range of output voltage, and the ISN diff-amp - a two-op-amp diff-amp of U25 - common-mode rejection (CMR) becomes a design consideration. For better CMR, R42 is nominally a 10.2 kΩ resistor, but for CMR maximization is replaced by R42, R100, R101. (The grounded pot terminal of R100 is connected to the wiper terminal.) Adjustment of the pot is made by varying the output voltage with an open-circuit output port so that the diff-amp has no differential input voltage across Rs (which additionally is set to the 1 Ω, near-short position of the 100 mA fs range). Adjust the R100 trimpot while varying the output voltage with the front-panel pot (with source switch set to V-source mode) until output voltage variations do not cause an appreciable change in the diff-amp output voltage, displayed as IISN on the DVM.
C, the display logic is processed by switches and diode logic. The switching for both the LED display decimal point (dp) and units LEDs uses the second wafer and pole of the 2P7T switch. Diodes are needed to logically combine LED drive from multiple switch settings. The INP (S1B) and OUT (S3B) ranges are the same and this allows their throw positions (switch output terminals) to be connected in parallel. The DVM input selector or display switch, S2 is the most complicated because it is a 4P2T toggle switch. Two of the four separate circuits (S2C and S2D) switch logic for dp and units LEDs and the other two are DVM input voltage selectors. The same kind of sequenced-stage logic is used for both DVM input selection as for display switching.
In the next part, we continue with the output port circuit.