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Keith Sabine

Electrically Correct Analog Layout

Keith Sabine
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Casquemodulable
3/20/2017 7:20:20 AM
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Although digital design productivity has improved massively since the introduction of synthesis, advanced place and route and timing-driven design, analog design still relies on circuit simulation, manual layout and verification.
On a conventional CMOS process, NMOS devices are formed in a P well or substrate connected to ground (or the most negative supply in the circuit). PMOS devices are formed in an N well connected to the most positive supply
Early CMOS processes suffered a reliability concern that became known as latchup. It resulted in circuits either malfunctioning or consuming excessive power, and could be either inherent in the design or triggered by voltage spikes on IO pads that could forward bias PN junctions they were connected to.
Analog designers have always had to worry about physical layout to get good matching of devices.
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