**Editor's note:** We will publish this article in four sequential parts leading up to our "Ask the experts" session on Precision Voltage References on May 21. Alan Walsh will be one of our experts.

The overall precision of a high-resolution, successive-approximation ADC depends on the accuracy, stability, and drive capability of its voltage reference. The switched capacitors on the ADC's reference input present a dynamic load, so the reference circuit must be able to handle time- and throughput-dependent currents. Some ADCs integrate the reference and reference buffer on chip, but these may not be optimal in terms of power or performance -- and the best performance can usually be achieved with an external reference circuit. This article looks at the challenges and requirements involved with the reference circuit design.

**Reference input**

A simplified schematic of a successive-approximation ADC is shown in Figure 1. During the sampling interval, the capacitive DAC is connected to the ADC input, and a charge proportional to the input voltage is stored on its capacitors. When the conversion starts, the DAC is disconnected from the input. The conversion algorithm successively switches each bit to the reference or ground. Charge redistribution on the capacitors causes current to be drawn from or sunk by the reference. This dynamic current load is a function of both the ADC throughput rate and the internal clock that controls the bit trials. The most significant bits (MSBs) hold the most charge and require the most current.

**Figure 1**

Simplified schematic of a 16-bit successive-approximation ADC.

Figure 2 shows the dynamic current load on the reference input of the AD7980, 16-bit, 1-MSPS, PulSAR successive-approximation ADC. The measurement was made by observing the voltage drop across a 500-Ω resistor placed between the reference source and the reference pin. The plot shows current spikes of up to 2.5 mA, along with smaller spikes spread over the conversion.

**Figure 2**

AD7980 dynamic reference current.

To supply this current, while keeping the reference voltage free of noise, place a high value, low ESR reservoir capacitor, typically 10 µF or more, as close as possible to the reference input. A larger capacitor will further smooth the current load and reduce the burden on the reference circuit, but stability becomes an issue with very large capacitors.

The reference must be capable of supplying the average current needed to top up the reference capacitor without causing the reference voltage to droop significantly. In ADC data sheets, the average reference input current is typically specified at a particular throughput rate. For example, the AD7980 data sheet specifies the average reference current to be 330 µA typical at 1 MSPS with a 5-V reference.

No current is drawn between conversions, so the reference current scales linearly with throughput, dropping to 33 µA at 100 kSPS. The reference -- or reference buffer -- must have low enough output impedance at the highest frequency of interest to maintain the voltage at the ADC input without a significant current-induced voltage drop.