Basic SAR vs Delta;-Sigma Architecture
Many high-performance data acquisition systems (DASs) used in instrumentation, medical equipment, industrial automation, and power-line monitoring demand wide bandwidth and precision signal measurements while simultaneously addressing tough space constraints, thermal, and power design challenges. System designers are also increasingly demanding scalable solutions to reduce cost and risk in their system development for fast time-to-market delivery of end products.
The successive-approximation register (SAR) converter architecture based on the charge redistribution capacitor digital to analog converter (DAC) array is inherently asynchronous. This permits fast control loop design with nearly zero latency or pipeline delay associated with the conversions. The big advantage with the delta;-sigma (Δ-Σ) converter architecture is that it's conventionally monotonic and uses an integrated modulator for oversampling and digital decimation filtering. It requires a global internal or external clock source to synchronize all the internal blocks, resulting in a latency or settling time issue.
Basic SAR Architecture
Basic Δ-Σ Architecture
As shown in Figure 1a, the SAR ADC samples the input signal once at each convert start edge and compares bit on each clock edge. It then adjusts the output of the digital to analog converter (DAC) through control logic until the DAC output very closely matches the analog input. It requires N-number of clock cycles from an independent external clock to implement a single N-bit conversion in an iterative manner.
In Figure 1b, the Δ-Σ ADC continuously samples the analog input signal at the frequency of the modulator and its conversion output is weighted average of series of samples. The basic oversampling modulator in Δ-Σ ADC spreads the quantization noise such that most of it occurs outside the bandwidth of interest. Higher resolution Δ-Σ ADC has a longer conversion time since it requires 2N samples to complete a single conversion.
The internal comparator noise and DAC linearity determines the accuracy of SAR ADC conversion, whereas the settling time (switching) of the integrator in the modulator determines the accuracy of the Δ-Σ ADC conversion. One of the challenges with the SAR ADC is that the driver amplifier needs to settle switching transient currents injected on its analog input during the acquisition time between the end of one conversion and the start of the next conversion.
The input bandwidth of SAR ADC (tens of MHz) is higher than the sampling frequency. The desired input signal bandwidth is typically within tens to hundreds of kHz; so the anti-aliasing is required to filter out unwanted aliases folding back to bandwidth of interest. In the case of Δ-Σ ADC, the desired input signal bandwidth is usually from DC to few kHz and input bandwidth of digital filter is lower than the sampling frequency of the modulator, so it relaxes the anti-aliasing requirements. The digital filter removes the noise outside the bandwidth of interest and the decimator then reduces the output data rate back to the Nyquist rate.
SAR ADCs are widely popular due to their ease of use, low power, small package and low cost, especially in multiplexed DASs. Δ-Σ ADCs are popular in industrial and audio applications for out-of-band rejection and its ability to reject the 1/f noise content close to DC (50/60Hz) when chopping is implemented. In this case, high resolution is traded for sampling rate of the ADC.
In part 2, we will continue the comparison between these two popular ADC architectures.