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Brian Bailey

FinFETs & Analog

Brian Bailey
SunitaT0
SunitaT0
7/29/2013 3:45:05 PM
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Master
Re : FinFETs & Analog
Scott Herrin, analog design engineer at Freescale Semiconductor, said in a Design Automation Conference panel on using FinFETs for analog circuits: "There are definitely things that I see and get enthusiastic by and there are also things that I get concerned about. The noticeable benefits are increased gain and reduced leakage. You do get the issue of quantized width."

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Brian Bailey
Brian Bailey
7/8/2013 2:25:57 PM
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Blogger
Re: Monte Carlo in design process
It is not clear to me how much variation can be expected in the fins. While the sizes of them are somewhat constrained by the fabrication processes, I dont know if we can expect less variation in them or not. An interesting question that is beyond my knowledge at this point.

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eafpres1
eafpres1
7/8/2013 9:39:16 AM
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Blogger
Monte Carlo in design process
@Brian--per Scott's comment "now one will have two levels of a schematic with each of the 16 transistors now having their own 16 transistor schematics"

You mention that 2-fin or 3-fin instances may be common.  Since these sum to form the "device level" effect, it seems to me you would have to add Monte Carlo simulation of the 3 fins to get the aggregate which would further lengthen run times.

Perhaps if the process ranges are constant the Monte Carlo could be done ahead of time, and an aggregate solution used as the feature model in higher level design?

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Scott Elder
Scott Elder
7/5/2013 12:48:13 PM
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Blogger
Quantization in Analog
Brian - I think simulation times will increase because today's single device will become a mutli-transistor composite device.  So where before one had a schematic with 16 transistors and one model to compute for each transistor, now one will have two levels of a schematic with each of the 16 transistors now having their own 16 transistor schematics.  A 16 model computation becomes a 256 model computation.

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