Few topics in electrical engineering have demanded as much attention over the years as the phase-locked loop (PLL). The PLL is arguably one of the most important building blocks necessary for modern digital communications, whether in the RF radio portion of the hardware where it is used to synthesize pristine carrier signals, or in the baseband digital signal processing (DSP) where it is often used for carrier- and time-recovery processing. The PLL topic is also intriguing because a thorough understanding of the concept embraces ingredients from many disciplines including RF design, digital design, continuous and discrete-time control systems, estimation theory and communication theory.

The PLL landscape is naturally divided into (i) low signal-to-noise ratio (SNR) applications like Costas carrier-recovery and time-recovery applications and (ii) high SNR applications like frequency synthesis. Each of these areas is further divided between (a) analog/RF continuous-time implementations versus (b) digital discrete-time implementations. The different manifestations of the PLL concept require careful attention to different usage, analysis, design and implementation considerations.

With so many good tutorials about PLLs available on the Internet and elsewhere today, a theoretically unifying development will be presented in this article with the intention of providing a deepened understanding for this extremely pervasive concept. In Part 1 of this series we'll look at PLL basics as well as different perspectives on PLL theory. In Part 2, we'll continue our look into PLL theory and then provide some real-world PLL design examples.

**PLL Basics**

The best way to develop a sound understanding of the PLL is to review the fundamental theories upon which this concept is based. One of the factors contributing to the longevity of the PLL is that relatively simple implementations can still lead to nearly optimal solutions and performance.

"While recovering from an illness in 1665, Dutch astronomer and physicist Christiaan Huygens noticed something very odd. Two of the large pendulum clocks in his room were beating in unison, and would return to this synchronized pattern regardless of how they were started, stopped or otherwise disturbed.

An inventor who had patented the pendulum clock only eight years earlier, Huygens was understandably intrigued. He set out to investigate this phenomenon, and the records of his experiments were preserved in a letter to his father. Written in Latin, the letter provides what is believed to be the first recorded example of the synchronized oscillator, a physical phenomena that has become increasingly important to physicists and engineers in modern times." (See http://www.globaltechnoscan.com/20thSep-26thSep/out_of_time.htm

It should come as no surprise that modern researchers would later find that the behavior of such injection-locked oscillators can be closely modeled based upon PLL principles.^{6,7,8,9}. Anyone who has tried to co-locate RF oscillators running at different but nearly the same frequency has experienced how incredibly sensitive this coupling phenomenon is!

In 1840, Alexander Bain proposed a fax machine that used synchronized pendulums to scan an image at the transmitting end and send electrical impulses to a matching pendulum at the receiving end to reconstruct the image. The device, however, was never developed.

"The phase-lock concept as we know it today was originally described in a published work by de Bellescize in 1932^{1} but did not fall into widespread use until the era of television where it was used to synchronize horizontal and vertical video scans. One of the earliest patents showing the use of a PLL with a feedback divider for frequency synthesis appeared in 1970.^{2} The PLL concept is now used almost universally in many products ranging from citizens band radio to deep-space coherent receivers."^{1}

A PLL consists of three basic components that appear in one form or another:^{4,5}

- Phase error metric or detector
- Frequency-controllable oscillator
- Loop filter

Loop "type" refers to the number of ideal poles (or integrators) within the linear system. A voltage-controlled oscillator (VCO) is an ideal integrator of phase for example.

Loop "order" refers to the polynomial order of the describing characteristic equation for the linear system. Loop-order must always be greater than or equal to the loop-type.

Although the term "settling time" is frequently used in the literature, a specified settling time is meaningless unless the definition for settling is also provided. A properly rigorous statement would be for example, "The settling time for the PLL is 1.5 ms to within +/-5 degrees of steady-state phase."

**Continuous-Time Versus Discrete-Time Systems**

PLL work was originally based upon continuous-time dynamics and engineers utilized the Laplace transform to mathematically describe linear PLL behavior. The world has however gone digital and with it, time has been discretized and dynamic quantities sampled. The connection between continuous-time and discrete-time systems can be easily bridged by making use of the Poisson Sum formula.^{3}. This formula relates the continuous-time function h(t) and its Fourier transform H(f) to the discretized world as:

where T_{s} is the time interval between samples. The left-hand side of Equation 1 is by definition the z-transform of h(t) weighted by the quantity T_{s}.

It is insightful to look at this statement for the classic type-2 third-order PLL shown in **Figure 1** for which the open-loop gain is given by:

*Figure 1: Diagram of a simple charge-pump PLL.*
where K_{V} is the VCO tuning sensitivity (rad/sec/V), K_{d} is the phase detector gain (A/rad.), N is the feedback divider ratio, and τ_{p} and τ_{2} are the time constants associated with the lead-lag loop filter. In this form, the loop natural frequency and loop damping factor are given respectively by Equations 3 and 4.

The discrete-equivalent z-transform for G_{OL}(s) can be computed as:

As developed at length in Chapters 4 and 5 of Reference 3, sampling control system factors adversely affect PLL stability, settling time, and phase noise performance as the closed-loop bandwidth is permitted to exceed approximately 1/10th of the phase comparison frequency. Sampling effects on the open-loop and closed-loop transfer functions can be assessed by either going to the trouble to first compute the z-transform of the open-loop gain function as in Equation 7, or the Poisson Sum formula can be used to compute the closed-loop transfer function much more conveniently as:

Only a very few of the aliased G_{OL}(s) gain terms need to be retained in the denominator in order to very accurately capture the sampling effects of interest.

The open-loop gain functions with and without the inclusion of sampling effects are shown in **Figure 2** assuming a sampling rate of 100 kHz, a natural frequency of 5 kHz and damping factor of 0.90. The closed-loop response for this same system is shown in **Figure 3** using Equation 8.

*Figure 2: Closed-loop gain showing continuous and sampled gain forms.*

*Figure 3: Closed-loop behavior for the case shown in Figure 2.*
If the PLL natural frequency is increased to 12.5 kHz (representing 1/8th of the sampling rate), stability problems become readily apparent as an excessive amount of gain-peaking that appears as shown in **Figure 4** and the almost nonexistent gain-margin as shown in **Figure 5**.

*Figure 4: Open-loop gain for increased PLL bandwidth case.*

*Figure 5: Closed-loop behavior for increased PLL bandwidth case. *
**PLL Theory Perspectives**

PLL theory of operation can be looked at from several different perspectives. As we have just seen in the previous section, time-continuous and sampled system analysis of PLLs used for frequency synthesis produce almost identical results unless the closed-loop bandwidth becomes an appreciable fraction of the phase comparison frequency being used.

In a similar fashion, different analysis must be used to study PLL operation under low signal-to-noise ratio (SNR) cases (e.g., customarily found in receiver applications) as compared to high SNR cases (e.g., like those encountered in frequency synthesizer usage). Several different perspectives that all help expand the phase-locked loop concept are discussed in the material that follows.

**Control Theory Perspective (High SNR)**

The control theory perspective of PLLs is normally the setting with which electrical engineers are dominantly familiar. Control theory concepts were used earlier in this article. Continuing in this vein, the classical type-2 second-order PLL that will be used for these discussions is shown in **Figure 6**. In our first view of this PLL in the strictly continuous-time domain, the phase detector is assumed to be linear (i.e., no sample-and-hold present).

*Figure 6: Classical type-2 second-order PLL with sample-and-hold phase detector.*

Several first-order approximations are helpful to keep in mind when dealing with this classical PLL system based upon simple Bode diagramming techniques. The open-loop gain diagram of interest is **Figure 7** whereas **Figure 8** pertains to the closed-loop characteristics. In both figures, the unity-gain radian frequency ω_{u} is given by Equation 11.

*Figure 7: Open-loop gain approximations for classic type-2 PLL.*

*Figure 8: Closed-loop approximations for classic type-2 PLL.*
As noted elsewhere, the behavior of real-world sampled systems matches the continuous-time behavior very closely if the system bandwidths are small relative to the sampling rate. Therefore, it is very convenient to use the results from continuous-time theory to approximate useful quantities for both types of systems. A number of these helpful results for the continuous-time case are provided in **Table 1**.

**Table 1 Helpful Formula for Classic Type-2 PLL**
*Click Here for Table 1*
In moving beyond the strictly continuous-time domain so that we can include digital dividers and phase detectors, we now include the zero-order sample-and-hold in the open-loop gain formula as given by Equation 12. In this formulation, K_{d} now has dimensions of V/rad. and T_{s} is the time between sampling instants. The closed-loop natural frequency and damping factor are still given by Equations 9 and 10 respectively.

In the case where the continuous-time open-loop gain is given by Equation 12, full sampling effects can be included by computing the equivalent z-transform for this open-loop gain function which is:

The system gain-margin G_{M} based upon Equation 13 can be shown to be:

But the gain margin is only defined provided that &omega

_{n}T<>sub>s < 4ζ. This same constraint applies for the system phase margin, which is given Reference 3. Since the z-domain shown in Equation 13 includes sampling effects whereas the Laplace s-domain in shown in Equation 12 does not, the gain-margin predicted using the Laplace transform G

_{OL}(s) will always be more optimistic than actual as shown in

**Figure 9**.

*Figure 9: Gain margin for classic type-2 PLL with sample-and-hold ζ=0.707.*
**Phase-Locked Loops for Low SNR Applications**

Low SNR applications are frequently observed at the receiving end of the system. The low SNR case can be cast in its most simple form as a simple sinusoidal signal immersed in additive white Gaussian noise (AWGN) and mathematically represented as:

where s(t)= A cos(ω_{o}t + θ) and the frequency and phase are considered constant. In the phase-lock condition, we can further assume that the frequency ω_{o} is known whereas the system is attempting to track the phase θ, which is assumed to be quasi-static relative to the bandwidth of the PLL tracking system. It can be shown that the probability density function for the θ estimate can be written as:

where γ is the receive SNR. The cumulative pdf using Equation can be numerically computed to create the traditional "S-curve" for the ideal phase error metric. Example probability density functions and their associated S-curves are shown in **Figures 10** and **11**.

*Figure 10: Phase error PDF.*

*Figure 11: Cumulative phase error PDFs (S-curves).*
Fokker-Planck techniques can be used to solve the ensuing closed-loop tracking performance question for type-1 PLLs.^{10,11,12}. The classic result that follows is the well-known Tikhonov probability density function for the closed-loop phase error given as:

where ρ is the SNR within the closed-loop bandwidth and I_{o}() is the modified Bessel function of order zero. A more insightful exploration into the tracking performance of the type-1 PLL can be made by using the S-curve results that were just presented along with a first-order Markov model for the system.

In the first-order Markov model for a type-1 PLL^{13,14}, the phase error range (-π,+π] is quantized across N states. Particularly nice closed-form results occur^{14} if the state transitions are limited to strictly nearest-neighbor transitions as shown in **Figure 12**. Since the use of N states divides the total phase range of 2π into N equally-spaced phase intervals, the closed-loop bandwidth is inversely proportional to N. The state-transition probabilities denoted by the p_{i} and q_{i} are directly obtained from the S-curve at the SNR of interest.

*Figure 12: First-order Markov chain model for type-1 PLL.*
The Markov steady-state probability equations can be formulated as:

in which the S_{k} denote the steady-state occupancy probabilities for each state with k=1...N. This set of equations can be solved as:

The mean tracking point and tracking error variance can be directly computed from the steady-state probabilities as:

The steady-state probabilities results are shown for two SNR cases with N=64 in **Figure 13**. The tracking error standard deviation for the SNR= -2dB case is 14.7 degrees rms whereas it is 9.9 degrees rms for the SNR= +2dB case **(Figure 14)**.

*Figure 13: Tracking error standard deviation (in degrees rms) and effective loop SNR (dB) versus input SNR (dB).*

*Figure 14: Steady-state probabilities).*
Another important quantity related to low SNR PLL operation is the quantity known as "mean-time to cycle-slip". This can be directly computed from the transition probabilities in a similar fashion as described in References 13 and 14.

**Minimum Variance Estimator**

The design of a near-optimal PLL can be investigated by considering the phase-tracking problem as a minimum-variance estimation problem. Assume that we have a received signal that is represented by:

in which n(t) represents complex Gaussian channel noise and s(t) represents a complex sinusoid as

If the received signal is discretized in time (t_{k} = kT_{s}), noise samples at t_{k} are assumed to be uncorrelated, and the estimates for the sinusoid's parameters are given by , the variance for the joint estimate is given by:

This can be expanded as:

Assuming that the PLL has already achieved frequency-lock, we will assume that and there is no frequency error present. Minimizing the estimator variance with respect to each individual parameter separately results in the following partial derivatives:

where is always a real quantity. The estimators that minimize the tracking error variance are then given as:

in which K is the total number of signal samples involved and z_{k}= exp(jωT_{s}). Although the estimator for involves first knowing , no prerequisite knowledge of is explicitly required in Equation 31 in order to find the best phase estimate. The implementation structure suggested by Equation 31 for the minimum-variance phase estimator is shown in **Figure 15**.^{19}

*Figure 15: Minimum-variance estimator cast as a PLL.*
**Maximum-Likelihood Estimator**

Another estimator form can be derived based upon maximizing probability or what is called "likelihood" in estimation theory. In the case of a real sinusoid of unknown phase in real additive Gaussian noise similar to the situation we just examined, we seek to pick an estimate for θ that maximizes the probability:

where and represent the K-dimensional measurement and signal estimate, and R is the KxK correlation matrix. In this real case being considered, s_{k} = A cos(ω_{o}kT_{s}+θ). We can equivalently seek to maximize the log-likelihood function of θ which is given by:

Assuming that the noise samples have equal variances and are uncorrelated, R= σ_{n2}I, where I is the KxK identity matrix. In order to maximize Equation 34 with respect to θ, a necessary condition is that the derivative of Equation 34 with respect to θ be zero, or equivalently:

Simplifying this result further and discarding the double-frequency terms that results, the maximum-likelihood estimate for θ is that value that satisfies the constraint:

The top-line indicates that double-frequency terms are to be filtered out and discarded. This result is equivalent to the minimum-variance estimator derived earlier in Equation 31.

**Wrap Up**

Diverse design perspectives can be utilized to improve and extend our basic understanding of the PLL concept. Mathcad worksheets for most of the results presented in this paper can be found at : http://www.siliconrfsystems.com/design_notes.htm.

In Part 2 of this article, we will close out the theoretical discussions by looking at (i) the maximum a posteriori (MAP) estimator PLL form, (ii) the Cramer-Rao bound which provides helpful insights into achievable theoretical performance, and finally (iii) the PLL derived based upon Kalman filtering concepts. The balance of the article will look at several real-world applications using the PLL concept. **Editor's Note: **To view Part 2, click here.

**References**

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*Frequency Synthesizer Design Handbook*, Artech House, 1994.
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*- Holmes, J.K., "Performance of a First-Order Transition Sampling Digital Phase-Locked Loop Using Random-Walk Models," IEEE Trans. Comm., April 1972.
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*Principles of Coherent Communication*, McGraw-Hill.
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*Digital Communication Receivers Synchronization, Channel Estimation, and Signal Processing*, John Wiley & Sons, 1998.
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*An Introduction to Statistical Signal Processing with Applications*, John Wiley & Sons, 1979.
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**About the Author**

**James Crawford** is the president/CEO and director of communication systems at Silicon RF Systems, Inc. Prior to this position, James served as the CTO of Magis Networks. He can be reached at jcrawford@siliconrfsystems.com.