Editor's note (December 22, 2010): some material was inadvertently left out of the original posting of this article. It has been added at the end of the main body of this part, below.Abstract
In designs requiring multiple op amps, the immediate, "obvious" tendency is to use duals or quads, and allocate the various sections based on pc board layout considerations. In many cases, no harm is done, but for some circuits, a careful choice of singles, duals or quads, and proper partitioning can improve circuit performance. This article discusses some common circuits and shows where two singles or one dual op amp is the proper choice.
One of the great insights of op-amp pioneer Bob Widlar was the realization that integrated circuits (IC) should be designed based on ratios and matching, rather than absolute values of resistors and transistors. This principle also can be applied when designing a printed circuit board (PCB) requiring multiple op amps.
Is a dual op amp really two op amps, or a piece of silicon with two functions?
There is a general belief that a dual op amp is the same as two singles, but there are some subtle differences between a monolithic dual IC and two singles on your board that may cause problems in your next design. Because the two op amps are side by side in the same monolithic piece of silicon, there are electrical and thermal factors to consider when using a dual.
The thermal effects have been know for over 30 years, and are well described in one of the top fifty cited IEEE papers by Solomon (Reference 1). As the op amp’s output voltage changes, the thermal dissipation changes, and a thermal wave propagates across the chip to the input stage, unbalancing it and appearing as an electrical signal. The thermal wave can affect both sections, even if they are electrically separate.
There are also electrical effects. In the desire to reduce die size, and therefore cost, some circuits, such as bias circuits and the associated start up circuit may be shared by both op amps. If one op amp operates outside of its normal range and causes the bias circuit to malfunction, then the other op amp will malfunction also (Reference 2). In addition, with a single pair of power pins, the bond wires and some metallization on the die carry the combined current of both op amps. Current drawn by one section will generate an IR drop that will be seen by the other op amp through the power supply rejection ratio (PSRR) specification which varies with frequency.
Nothing in life is free, so there are advantages and disadvantages to using duals. Some of the advantages are rather straightforward:
- First, a single insertion instead of two insertions will reduce manufacturing cost.
- Second, most semiconductor manufacturers generally price duals lower than twice the cost of a single op amp. By merging subcircuits, the die area is generally smaller than two times a single op amp.
- Third, high speed Automatic Test Equipment (ATE) is limited by handling time for simple functions such as op amps, so the test cost per function is also lower. Similar comments can be made for package costs.
- Finally, because the two circuits were very close on the wafer, the match of electrical characteristics between the two, unusually not specified, is very close.
There are some disadvantages, though. By putting two or four functions in one package, the power dissipation is increased. For low bandwidth, low voltage op amps, (low power dissipation) this increase results in a minor (5°C) increase in junction temperature. For high speed op amps, driving a low impedance load, such as a coax cable, this can be significant, perhaps 30°C. Due to die stress, the maximum offset voltage for quads will be higher than for duals or singles (Reference 3). In some cases, the dual will have higher offset than the single, and the quad will have higher offset than the dual (Reference 4).
Crosstalk is also a problem and comes from two effects: thermal and electrical. As mentioned earlier, the thermal wave from one section will unbalance the input stage of the other section. This appears as low frequency feedback. In addition, with one set of power supply pins, the bond wire resistance is common to all sections, so heavy load current from one section will cause an IR drop across the bond wires. The PSRR of the op amp is not infinite, so some portion will be coupled to the other sections. The PSRR decreases with increasing frequency, so look for this above 5 to 10 kHz.
To understand exactly why these effects occur, it is instructive to look at how singles, duals, and quads are constructed.
The input stage
A differential pair is usually the first stage of an op amp. It could be bipolar, either NPNs as shown, or PNPs. It could also be N-channel or P-channel MOSFETs, or N-channel or P-channel JFETs.
There is a common problem: if one side is at a different temperature than the other, even a tenth of a degree, the stage will be unbalanced. With a gain of 100,000 or more, this has an effect on the output voltage. When the output stage dissipates power, a thermal wave travels across the die to the input stage. If the input stage is far away, (relatively speaking), the isothermal lines will approximate parallel lines. If the two input transistors are positioned in such a manner so that the wave reaches both transistors at the same time, the balance will be little affected.
This is a good idea, but we can do better. By splitting the transistors in two, and cross-coupling them, a thermal wave at an angle will affect both sections less than if there were only two. Probably this was first used by George Erdi in the uA725 (Reference 5). The phrase “cross-coupled quad” has several meanings; this is the most common one. The output transistors and input transistors should be along the centerline as shown in Figure 1.
Figure 1 (Click on image to enlarge)
There are many other layout considerations with respect to die stress, temperature coefficient of resistors, etc. that are well covered by Hastings (Reference 6).
The layout in Figure 1 works well for a single op amp, but a problem arises with the dual op amp. The standard pin out for a dual is shown in Figure 2.
At the transistor level, one possible floorplan for a dual is shown in Figure 3. There is one problem: The output of channel B has to be routed over the input lines to get to pin 7. In the very early days, bipolar analog processes were single layer metallization and “cross-unders” had to be used, which affected the performance.
Figure 3 is a good layout for duals. The input stage is very close to the center of the die, so the mechanical stress gradient is minimized. The distance from one output stage to the other input stage is greater than the alternate layout. The isothermals from the output stage to both of the input stages are approximately parallel and equally spaced, so the rejection by the cross coupled input stage quad is very good.
The one major disadvantage is that the output B has to cross over both inputs to get to the output pad. Any capacitance from the output metalization to the noninverting input metalization results in positive feedback. This was more of a problem years ago with single layer metalization (SLM), but was ameliorated by the low gain bandwidth of those op amps. This layout is good thermally, but presents a problem if a quad version of the same family is planned.
There is another choice for a dual layout, as shown in Figure 4.
This is used if a quad is planned in the family, because the layout can be replicated and flipped vertically to quickly generate the quad layout. The inputs and outputs are reasonably close to the correct package pins. The standard pinout for a quad op amp is shown in Figure 5.
Figure 5 (Click on image to enlarge)
There are several subtle problems with this layout:
1) The input stages are not in the center of the die, which would be the lowest mechanical stress gradient point and lowest offset after packaging.
2) the distance from the output stage to the input stage is not as great as it could be, and
3) the thermal wave from one output stage to the other input stage has curved isotherms which are incompletely rejected by the cross coupled input pairs, resulting in crosstalk from one channel to the other.
This presents a dilemma: The optimal layout for a dual is not the optimum layout for a quad. Individual layouts could be done from scratch for every single, dual or quad, but with the focus on time to market and development costs, the standard procedure is to reuse as much of one design as possible. When only singles and duals are done in a family, the dual layout is usually optimized. As an interesting aside, note that if Figure 3 is flipped horizontally, the same quad layout results, so a quad will always have worse specs than a properly laid out dual or single.
Years ago, one manufacturer made a quad op amp that had very good specifications. The secret was the use of a special lead frame to accept two dual dice, i.e., a hybrid part or a multichip module (MCM). This requires either an in-house assembly operation or a close working relationship with an outside assembly house. The final yield is approximately the product of the individual die yields. For example, if the yield is 99%, then the final yield would be:
0.99 × 0.99 = 98.01%,
which is quite acceptable. On the other hand, if the yield is 90%, which is quite possible for parts with very tight specifications, then the overall yield is 0.9 × 0.9 = 81%.
Material added Dec. 22, 2010:
Finally, because of technical considerations, the number of singles offered is greater than the number of duals; the same is true for duals vs. quads, as shown in Table 1.
Note that the totals were obtained from the manufacturer’s websites in December 2009 and include commodity op amps, audio amplifiers, high speed, parts with and without shutdown pins (counted as two), and unity gain stable and decompenstated parts. In the precision area, such as low offset voltage or low noise, the totals would be more skewed toward singles and duals.
looks at good and bad examples as well as power-rail monitoring)
- Solomon, James “The Monolithic Op Amp: A Tutorial Study,” IEEE JSSC Vol. SC-9, No. 6 Dec. 1974
- Page 9, LT1013 datasheet at http://www.linear.com
- Page 2, http://cache.national.com/ds/LM/LMV774.pdf
- Page 2, http://datasheets.maxim-ic.com/en/ds/MAX4162-MAX4164.pdf
- Pease, Robert “What’s all this Common-Centroid stuff, anyhow?" http://www.national.com/rap/Story/0,1562,29,00.html
- Hastings, Alan “Art of Analog Layout” 2nd Ed., copyright 2005, Prentice Hall
- Pallás-Areny, Ramón and Webster, John G. “Common Mode Rejection Ratio in Differential Amplifiers,” IEEE Transactions On Instrumentation and Measurement, Vol. 40, No 4, August 1991, pp 669-676
- Wong, James “Active Feedback Improves Amplifier Phase Accuracy,” AN-107 at http://www.analog.com
- Soliman, Ahmed M, “Design of High-Frequency Amplifers,” IEEE Circuits and Systems, June 1983.
- Soliman, AM and Ismail, M, “Active Compensation of Op Amps,” IEEE Transactions on Circuits and Systems, February 1979
About the author
Harry Holt is a senior applications engineer at Analog Devices, Inc. in the precision amplifier group, where he has worked for three years. This follows 27 years in both field and factory applications at National Semiconductor for a variety of products, including data converters, op amps, references, audio codecs, and FPGAs. He has a BSEE degree from San Jose State University and is a life member of Tau Beta Pi and a Senior Member of the IEEE.