In July of 2011, the second and current revision of the standard was released, called JESD204B. One of the key components of the revised standard was the addition of provisions to achieve deterministic latency. In addition, the supported data rates were pushed up to 12.5 Gbps, with different speed grades of devices being described.
This revision of the standard calls for a transition from using the frame clock as the main clock source, to using the device clock as the main clock source. Figure 3 is a representation of the additional capabilities added by the JESD204B revision.
Figure 3: Second (Current) Revision – JESD204B
In the previous two versions of the JESD204 standard, there were no provisions defined to ensure deterministic latency through the interface. The JESD204B revision remedies this issue by providing a mechanism to ensure that, from power-up cycle to power-up cycle and across link re-synchronization events, the latency should be repeatable and deterministic.
This is accomplished by initiating the initial lane-alignment sequence in the converter(s) simultaneously across all lanes, at a well-defined moment in time by using an input signal called SYNC~. In addition, the receiver must have each lane of data buffered to account for skews across the serial data lanes. These buffers should be released simultaneously, also at a well-defined moment, in time by using a programmable number of cycles referred to as the Rx Buffer Delay (RBD).
In addition to the deterministic latency, the JESD204B version increases the supported lane data rates to 12.5 Gbps, and divides devices into three different speed grades:
•The first speed grade aligns with the lane data rates from the JESD204 and JESD204A versions of the standard, and defines the electrical interface for lane data rates up to 3.125 Gbps. As mentioned earlier, the differential-voltage level for these data rates is nominally 800 mV peak-to-peak, with a common-mode voltage-level range from 0.72 V to 1.23 V (with both source and load impedance defined as 100 ? ±20%).
•The second speed grade in JESD204B defines the electrical interface for lane data rates up to 6.375 Gbps. This speed grade is similar to the first speed grade, in that the differential voltage level is nominally 800 mV peak-to-peak. The common-mode voltage-level range has some slight differences based on the termination voltage specified at the receiver, but is generally similar to the first speed grade. The source and load impedance is the same, with both defined as 100 ? ±20%.
•The third speed grade in JESD204B defines the electrical interface for lane data rates up to 12.5 Gbps. This speed grade lowers the differential voltage level required for the electrical interface to 400 mV peak-to-peak nominally, which effectively reduces the required levels by a factor of two when compared to the lower two speed grades. The common mode voltage level range is similar to the second speed grade and depends on the termination voltage specified at the receiver. Once again, both source and load impedance is defined as 100 ? ±20%.
To allow for more flexibility, the JESD204B revision transitions from the frame clock to the device clock. Previously, in the JESD204 and JESD204A revisions, the frame clock was the absolute timing reference in the JESD204 system. Typically, the frame clock and the sampling clock of the converter(s) were usually the same.
This did not offer a lot of flexibility, and could cause undesired complexity in system design when attempting to route this same signal to multiple devices and account for any skew between the different routing paths. In JESD204B, the device clock is the timing reference for each element in the JESD204 system. Each converter and receiver receives their respective device clock from a clock-generator circuit which is responsible for generating al device clocks from a common source. This allows for more flexibility in the system design, but requires that the relationship between the frame clock and device clock be specified for a given device.
As the speed and resolution of converters have increased, the demand for a more-efficient digital interface has increased. The JESD204 serialized data interface has been created to offer a better and faster way to transmit data from converters to receiver devices.
The interface has undergone two revisions to improve its implementation and meet the increasing demands brought on by higher-speed, higher-resolution converters. Each revision has answered the demands for improvements on its implementation, and has allowed the standard to evolve to meet new requirements brought on by changes in converter technology. As system designs become more complex and converter performance pushes higher, the JESD204 standard is poised to adapt and evolve to continue to meet the new design requirements necessary.
References (all are JEDEC Solid State Technology Association, http://www.jedec.org)
- JEDEC Standard JESD204 (April 2006)
- JEDEC Standard JESD204A (April 2008)
- JEDEC Standard JESD204B (July 2011)
About the author
Jonathan Harris is a product applications engineer in the high speed converter group at Analog Devices in Greensboro, NC. He has over seven years of experience as an applications engineer supporting products in the RF industry. Jonathan received his MSEE from Auburn University and his BSEE from UNC-Charlotte. In his spare time he enjoys mobile audio, nitro R/C, college football, and spending time with his two children.
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