As the resolution and speed of converters has increased, the demand for a more efficient digital-side interface has grown. Currently, analog to digital converters (ADCs) are migrating from parallel LVDS (low-voltage differential signaling) and CMOS digital interfaces to a serialized interface called JESD204, developed by JEDEC (http://www.jedec.org/, formerly known as the Joint Electron Device Engineering Council, see http://www.jedec.org/about-jedec/jedec-history for historical background).
The JESD204 interface brings this efficiency while offering several advantages over its predecessors in terms of speed, size, and cost. Designs employing JESD204 enjoy the benefits of a faster interface to keep pace with the faster sampling rates of converters. In addition, there is a reduction in pin count, which leads to smaller package sizes and a lower number of trace routes, both of which make board designs much easier and offer lower costs in packaging and board designs.
The standard is also easily scalable so it can be adapted to meet future needs, as has been exhibited by the two revisions which the standard has already undergone. The JESD204 standard has had two revisions since its introduction in 2006 and is now at revision B.
As the standard has been adopted by converter vendors and users, it has been refined and new features have been added that have increased efficiency and ease of implementation. The standard applies to both analog to digital converters as well as digital to analog converters (DACs); however, the focus in this article will be on its application to ADCs.
In April of 2006, the original version of JESD204 was released. The standard describes a multi-gigabit serial data link between converter(s) and a receiver, commonly a device such as an FPGA or ASIC. In this version, the serial data link was defined for a single serial lane between a converter or multiple converters and a receiver.
A graphical representation is provided in Figure 1. The lane shown is the physical interface between M number of converters and the receiver, where the interface consists of a differential pair of interconnects using current mode logic (CML). The link shown is the serialized data link that is established between the converter(s) and the receiver. The frame clock is routed to both the converter(s) and the receiver and provides the clock for the JESD204 link between the devices.
Figure 1: JESD204 Original Standard
The lane data rate is defined between 312.5 Megabits per second (Mbps) and 3.125 Gigabits per second (Gbps) with both source and load impedance defined as 100 ? ±20%. The differential voltage level is defined as being nominally 800 mV peak-to-peak with a common-mode voltage level range from 0.72 V to 1.23 V. The link utilizes 8b/10b encoding which incorporates an embedded clock, removing the need to route an additional clock line, and the associated complexity of aligning an additional clock signal with the transmitted data at high data rates.
This form of serial data transmission allows the trace-to-trace tolerance to be relaxed, relative to synchronous-sampling parallel LVDS and CMOS interface designs. In addition, the encoding is DC balanced, which guarantees a significant transition frequency for use with clock and data recovery (CDR) designs.
The encoding also allows for the use of data and control characters which specify link alignment, maintenance, and monitoring. The standard specifies training patterns with these control characters that allow the lane to be aligned between the converter(s) and the receiver across the link.
The quality of the link is monitored in the receiver, and the link is established and dropped by the receiver based on certain error thresholds defined by the JESD204 standard. The standard was revised when proponents saw that it needed to incorporate support for multiple, aligned serial lanes with multiple converters, to accommodate increasing speeds and resolutions of converters.
In April of 2008, the first revision of the standard was released, designated JESD204A. This revision of the standard added the ability to support multiple aligned serial lanes with multiple converters. The lane data rates which it supported remained unchanged from the original version of the standard, from 312.5 Mbps up to 3.125 Gbps, and the frame clock also remained.
Increasing the capabilities of the standard to support multiple, aligned serial lanes made it possible for converters with high sample rates and high resolutions to meet the maximum supported data rate of 3.125 Gbps. Figure 2 shows a graphical representation of the additional capabilities added in the JESD204A revision to support multiple lanes.
Figure 2: First Revision – JESD204A
By adding these capabilities to the standard, converters with higher sample rates and/or higher resolutions could be supported. For example, a 14-bit ADC operating with a sample clock of 250 MHz would require an output data rate of 5.0 Gbps when transmitting over one link with one lane as described in JESD204.
However, with the revision to JESD204A, the standard now supported multiple aligned serial lanes and the converter samples could be mapped onto two aligned serial lanes. This would lower the data rate to 2.5 Gbps per lane, which is below the maximum supported data rate of 3.125 Gbps.
When dealing with an ADC, it is important to know the timing relationship between the sampled signal and its digital representation, in order to properly recreate the sampled signal in the analog domain once the signal has been received. Although both the original JESD204 standard and the revised JESD204A standard were higher performance than legacy interfaces, they were still lacking in one key element: deterministic latency in the serialized data on the link.
This timing relationship is affected by the latency of the ADC, which is defined as the number of clock cycles between the instant of the sampling edge of the input signal, until the time that its digital representation is present at the ADC’s outputs. In the JESD204 and JESD204A standards, there were no defined capabilities that would deterministically set the latency of the ADC and its serialized digital outputs. In addition, converters were continuing to increase in both speed and resolution. These factors led to the introduction of the second revision of the standard, JESD204B.