In current implementations of both systems, the multi-gigabit
serializing function is typically performed by a relatively high end
FPGA. Moving the FPGA from the front end of designs and enlisting the
JESD204B ADCs presents clear benefits. For a system such as a cable
transmitter, for example, the FPGA is removed from each of the remote
transmitting sites – saving cost and power -- because the transmitter no
longer requires it. For a radar system, to note another example, moving
the FPGA from the space-constrained ‘front’ of the design to the more
flexible ‘back-end’ is the only way to lay out the entire receive chain,
from RF to digital to optical, within limited space allowed. (In both
of these applications, FPGAs are required on the receiving end of the
system and remain a vital part of the design.)
The alternative
Intersil
has used its family of 12- to 16-bit JESD204B ADCs to develop a
reference design that brings these reduced size, cost and power benefits
to users. Using Avago fiber optic transceiver evaluation boards,
several transmitting options have been demonstrated including the
following: two-channel 14-bit ADC using two fibers; two-channel 12-bit
ADC using one fiber; and one-channel 14- and 16-bit ADCs using two
fibers. To receive and analyze the data, Intersil’s Xilinx Virtex-5
based JESD204B receiver reference design is used. Please refer to Figure 1 for a sample block diagram of this system.
Among the kinds of designs that can benefit are these:
- Cable
Digital Return, Radio-over-Fiber, Antenna Array Processing: data is
digitized, serialized, and then transmitted over a fiber cable.
JESD204B high speed ADCs can eliminate the need for a dedicated
serializer function (eliminates or cost-reduces the FPGA).
- Communications
Infrastructure: Base-stations and remote radioheads often require
multiple receivers. Using a serial interface from ADC to FPGA
simplifies the physical design, as long as the high-speed serial
connection offers a constant latency. JESD204B ADCs provide the serial
connection and solves the problem of uncertain latency.
- General
Purpose I/O & Digitizer Modules: modular I/O cards are often used in
a mix-and-match approach where an I/O card plugs into a data collection
board. These are often limited by the number of pins in the
connector. I/O devices using high-speed serial interfaces allow for a
higher number of I/O channels.
The optical transmission of
JESD204B ADC outputs can be accomplished using off-the-shelf fiber optic
evaluation components and Intersil’s JESD204B ADC evaluation platform.
Referring to
Figure 1, one implementation that has been
demonstrated to be effective digitizes two inputs using the ISLA222S, a
2-channel, 12-bit 150MSPS ADC with one serial output.
The
serial output of the ADC drives the TX input of an Avago fiber optic
transceiver evaluation board. The fiber optic transceiver converts the
4.5 Gbps electrical data stream to optical and transmits it over the
fiber to a second Avago fiber optic transceiver, which converts it back
to electrical. The transceiver’s RX output is wired to Intersil’s
JESD204B motherboard where the data is de-serialized and displayed using
Intersil’s JESD204B receiver reference design.
While high-speed
serial interfaces are known to offer significant advantages, in the
minds of many designers, they still come with implementation risks that
are perceived to be high. But the standardization of the interface, in
fact, reduces the adoption risk.
As demonstrated here, devices
that can support the JESD204B interface, even from varied suppliers such
as Intersil, Avago and Xilinx can be quickly connected together to
realize the immense benefits offered by high speed serial interconnect.
Click on image to enlarge.
Figure 1. Block Diagram with ISLA222S driving the TX input of an Avago fiber optic transceiver evaluation board.
--Edward Kohler
is Senior Strategic Marketing Manager for High Speed Data Converters at
Intersil Corporation. He has worked in high-speed ADC design and
marketing for eight years. He earned his BSEE degree from Michigan
Technological University, his MSEE degree from the University of
Michigan, and his MBA degree from Yale University.
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