As the sample rate and resolution of todayís data converters increase, new high-density techniques for the digital data interface are being developed to cope with the large number of signals and high data transmission rates.
High-speed serial interfaces offer numerous advantages over traditional parallel interfaces. But they can be challenging to implement for even the most proficient designers. While many system developers and designers acknowledge the enormous potential value they perceive increased risk and become reluctant to adopt the technology -- even though existing solutions in many cases are more expensive and need more real estate and power.
[Get a 10% discount on ARM TechCon 2012 conference passes
by using promo code EDIT. Click here to learn about the show and
The benefits of these new interfaces are significant. A high-speed serial interface offers a significant reduction in the number of data and clock signals. This translates into fewer I/O pins, less PCB routing, and relaxed physical design constraints. In addition to these obvious benefits are system-level advantages.
For instance, a hybrid fiber/coax network consists of hundreds of remote sites that convert data from coax to fiber and send it back to one central office. At each remote site, an ADC (analog-to-digital converter) digitizes signals from the coaxial cable. The ADC outputs are serialized and then broadcast over fiber via an optical transmitter. This can be implemented with a traditional (parallel) ADC -- and some designers are doing so. But the design requires an additional element between the ADC and fiber optic transmitter to serialize the data, which is often expensive and space consuming.
Now, there is an alternative. Using an ADC with JESD204B-complaint high-speed serial outputs, designers can remove the dedicated serializing device, reducing the transmitterís size and power consumption. This is possible because JESD204B data can be directly broadcast over fiber. In many cases, adopting a device with a new standard would be perceived as risky, but this simplified architecture can be prototyped and demonstrated using standard off-the-shelf evaluation kits of the JESD204B ADC and fiber-optic transmitter, no additional encoding, level translating, or serializing operations are required. Benefits of the JESD204B standard
JESD204, a high-speed serial interface standard for data converters was initially introduced in 2006. It has evolved through three generations, JESD204, JESD204A, and JESD204B, with each revision enhancing the prior version.
Two features critical to adoption in the communications and multichannel ADC markets were included in the B version. First, JESD204B provides deterministic latency in mapping from the convert clock to the serial data output, allowing consistent data latency after every reset. Second the B version of the standard increases the maximum data rate, providing for efficient use of fewer I/O resources.
For instance, the B standard allows a dual 14-bit 250Msps ADCs to use only one serial lane per channel. Devices restricted to the ĎAí version data rates would require two lanes per channel, doubling the I/O resources required. While the latency uncertainty and low data rates of the A standard impeded wide JESD204 adoption, the B standard will accelerate this important step forward, beginning in communications and/or multi-channel converter applications.
Simplifying the system architecture
Since these leading edge ADCís perform the serializer operation, it is now possible to eliminate dedicated serializing devices from some system designs, reducing space, power, and cost. Start with the hybrid fiber/coax transmitter described above.
Traditionally, this system consists of an ADC, connected to an FPGA, connected to a fiber optic transmitter. The FPGA packetizes and serializes the data from a parallel output ADC. But using ADCs with JESD204B outputs, it is possible to remove the FPGA and connect the ADC output directly to the fiber optic transmitter. This removes cost and power from what is often a remote site, and shrinks the entire assembly.
Similarly, consider a radar system that must transmit signals roughly 100 meters from an array of densely spaced receiving elements to a centralized DSP. Each elementís physical dimensions are constrained by the antenna design. This requires a very small form factor for each element's receive chain, typically including a filter, amplifier, ADC, and transmitter. Typical ADC outputs (LVDS/CMOS) can't be transmitted more than a few feet at most. This means that the outputs must be converted in some way in order to transmit them longer distances. Fiber optics are the obvious solution for transmitting digital data long distances, as long as the ADC data can be serialized and converted to optical -- within the space constraints.
The level of noise produced by the aliasing effect during the sampling process can be reduced in two steps of the signal chain. The inclusion of the anti-aliasing filter, combined with over-sampling and decimation, are effective mitigation techniques.
Over the years, the introduction of more complex tools has enabled much more capability in the circuit simulation arena. These new tools enable exploring circuit interaction to arrive at solutions to complex issues.