ADC Basics (Part 4): Using delta-sigma ADCs in your design

The delta-sigma ADC tackles the application demands of a slow analog signal that requires a high signal-to-noise-ratio (SNR) and wide dynamic range. But, the delta-sigma converter is not the only device that tackles these application requirements. You will find that designers also utilize SAR-ADCs in these lower frequency applications.

The SAR-ADC system usually requires an analog gain stage and a complete anti-aliasing filter, where the delta-sigma converter does not require these external functions. The delta-sigma converter has much of the required signal conditioning functions designed within the chip and performs these functions in the digital domain. As a matter of fact, the delta-sigma ADC can nearly be considered as a system-on-a-chip (SoC).

In this article, we investigate the position of the delta-sigma converter in the signal chain circuit, the overall operation of the delta-sigma converter, the delta-sigma noise shaping phenomena, and the utilization of process gain within the delta-sigma converter. Although this article does not provide a comprehensive treatment of the delta-sigma converter, we use these concepts as we compare the SAR-ADC and delta-sigma converter at the system level.

Delta-sigma ADC signal chain
The signal chain for the delta-sigma converter application starts with the sensor (left side of Figure 1). Contrary to a typical SAR-ADC system, there are no analog gain circuits, such as an amplifier and instrumentation amplifier, following the sensor block. Between the sensor and the delta-sigma converter, there is an anti-aliasing, low-pass filter. The delta-sigma converter and the SAR-ADC anti-aliasing filter designs are significantly different. With a SAR converter, the anti-aliasing filter usually has an active fourth to eighth order implementation, requiring two to four amplifiers. As Figure 1 shows, the delta-sigma anti-aliasing implementation generally requires only a first order, passive filter _[1].

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Circuit designers find the simplicity of this signal chain attractive. The required external elements are the passive, anti-aliasing components and the voltage reference.

Delta-sigma internal modules
The core of the delta-sigma converter has an analog modulator, followed by a digital / decimation filter (Figure 2). For most kinds of ADCs, the data rate and sampling rate are the same; each input sample converts to one output code. In contrast, the delta-sigma, acquires many input samples to produce one output code. This delta-sigma sampling algorithm lengthens the acquisition time.


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While most converters have only one sample rate, the delta-sigma converter actually has two: the input sampling rate, Fs (based on the modulator clock); and the output data rate, Fd (a fraction of the modulator clock). The Fd value is the corner frequency of the internal digital/decimator filter. One uses Fd to define the corner frequency of delta-sigma converter’s external anti-aliasing filter.

In Figure 2, the delta-sigma’s modulator samples and quantizes the input signal in a coarse fashion, by producing a one-bit stream of data at a very high rate _[2]. Unlike most quantizers, the delta-sigma modulator includes an integrator, which has the effect of shaping the quantization noise.

Noise shaping and using the decimation ratio
The output of the modulator in the time domain signal looks uneventful. Averaging this signal produces the value of the input signal. The frequency domain representation shows a different story. In the frequency domain, the accumulated modulator output data creates the input signal, with most of the noise shaped into frequencies above the input signal frequency.

The following digital / decimator (low-pass) filter preserves the input signal as well as attenuates this higher frequency noise. It also takes this sampled modulator data and converts it into a precise digital signal _[3].