One can view the SAR-ADC as a one-shot converter where the output data represents a single analog sample.
Figure 3
illustrates a possible delta-sigma converter timing scenario. In this
figure, the converter acquires multiple samples and internally produces
intermediate conversions.
Click on image to enlarge.
Figure 3. 24-bit delta-sigma conversion timing diagram using the ADS1258.
This
figure shows the intermediate, internal conversions of the delta-sigma
converter with a fifth-order digital filter. Notice the “hidden
conversions” are an artifact of the internal digital filter’s order. The
user never sees these hidden conversions.
Output noise
The
noise magnitude produced by the SAR-ADC and delta-sigma converter, as
compared to the number of bits, is dramatically different. Typically,
the noise generated by the 12-bit SAR-ADC is well below the voltage size
of the converter’s LSB. For instance, a 12-bit SAR-ADC with a 4.096V
full-scale input range has an LSB size of 1 mV. In contrast, a 24-bit
delta-sigma converter with a 4.096V full-scale input range has an
approximate LSB size of 244 nV.
Device or converter noise is a random event, but it does follow probability theories.
Figure 4 illustrates a group of a delta-sigma converter results with a DC input. There are three points of interest.
Click on image to enlarge.
Figure 4. Continuous output data from a delta-sigma converter.
First
is the mean value. The mean, or average value of the data, is a
reference point needed when you calculate the data’s standard deviation.
The second point of interest is the volts-RMS or bits-RMS label. These
labels are equivalent to a span from the data’s negative to the positive
standard deviation. Third, if you are going to place the converter
results in a display, volts p-p or bits p-p determine how often the
lower digits in your display change.
Figure 5 shows how
the output data in Figure 4 translates into a histogram. The RMS value
is equal to the standard deviation of this data. Between the two
standard deviations or RMS lines in this graph, a significant number of
the noise occurrences are captured. The probability that an ADC produces
one output value that lands between the two RMS lines is equal to about
68 percent.
Click on image to enlarge.
Figure 5. Unipolar Ideal ADC Transfer Function
With
the Gaussian distribution in our histogram plot, you can see that your
RMS limits exclude a lot of data. If you look at the number of converter
output results between the two standard deviation limits, you account
for 68 percent of the occurrences. But if you multiply the doubled
standard deviation by a constant or crest factor, you can expand the
percentage of occurrences underneath the curve. The crest factor allows
you to define your peak-to-peak limits as well as determine which of the
converter bits are useful in your 12-bit system.
Conclusion
The
discussion in the article excludes a signification number of ADC
specifications. These other specifications are important as you hone in
on your finished solution, however, the topics mentioned here can be
used to quickly prove or disprove the appropriate direction for your
system design. The 12-bit applications that we are exploring include
multiplexed circuits, handheld meters, data loggers, automotive systems,
and monitoring systems.
References
1. “
A Glossary of Analog-to-Digital Specifications and Performance Characteristics (SBAA147B),” B. Baker, Texas Instruments, October 2011.
2. “
Delta-sigma ADCs in a nutshell, part 3: the digital/decimator filter,” Baker, EDN, February 21, 2008.
For more information, see
Part 4 and
links to Parts 1,2,3 here.
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