There are many things that affect the performance of electronic circuits. Certainly, the choice of the various components is important, but so are other things, such as circuit topology and signal integrity.
The issue of signal integrity has become a popular topic in light of the very high edge rates that have resulted from today's technology. Working with today's high-speed digital signals has meant that digital designers must be concerned with signal integrity, something that was once considered to be of concern only to analog engineers, or even limited to Radio Frequency (RF) engineers.
As we strive for faster and faster data signaling rates, it becomes necessary that our circuitry provide faster and faster edge rates, or rise and fall times. The problem occurs when the distance the signal must travel is significant when compared with the time of travel of a signal edge down a line and back. Various authors have given differing numbers for this rate, but the rate of propagation depends upon the dielectric constant of the board material and whether we are talking of a completely buried trace or one that remains on the surface of the board.
The issues of signal integrity are not at all limited to digital circuitry, but are applicable to analog and mixed-signal circuits as well. Analog signal fidelity issues can often be traced to signal integrity problems. Since mixed-signal devices, such as Analog-to-Digital Converters (ADCs or A/Ds) and Digital-to-Analog Converters (DACs of D/As) have both analog and digital circuitry and signals associated with them, they can be considered to suffer a "double whammy" in the signal integrity arena.
While this article specifically addresses the problems experienced with mixed-signal components, using an ADC as an example, these principles can be equally applied to analog and to digital circuitry.
The scope of the problem
Signal Integrity concerns are paramount these days and we are constantly in search of ways to ensure the integrity of our signals and the adequacy of our interconnects. Most approaches rightfully come from a firm grounding in the fundamentals of electronic communications, but often get "hung up" with the mathematics of the solution.
While mathematics is extremely helpful for this understanding, engineers generally know the math involved and only need a review of the basic fundamentals to understand what is happening and how to achieve the communications accuracy they seek. Because of this, the approach here is to minimize the mathematics involved and rely upon a discussion of the basic, underlying principles, then relate those principles to circuit layout and grounding.
The proximity effect
The fundamental principle that describes the behavior of electrical currents and the electromagnetic fields associated with them is the Proximity Effect. Understanding this phenomenon helps us to establish what is necessary in the way of layout and circuit design to ensure signal integrity and to minimize EMI/RFI (Electromagnetic Interference/Radio Frequency Interference) problems.
We know that current seeks the path of least impedance. What we often do not think about is the relationship between outgoing and return current proximity and the path impedance.
AC current flow requires the establishment and maintenance of a magnetic field. The larger the electromagnetic field around the outgoing and return paths, the more the energy required to establish and maintain this field, resulting in a higher signal path impedance. If the outgoing and return currents could somehow remain very close to each other, the electromagnetic field around this current loop would be fairly well confined. The field around this confined current loop requires a relatively small amount of energy to establish and maintain, so the path impedance is lower. This means that the AC outgoing and return currents will attempt to remain as close to each other as possible. We call this the Proximity Effect because AC outgoing and return currents want to remain in close proximity with each other.
When currents diverge
If the outgoing and return current paths are forced to diverge from each other, the path impedance will increase. Furthermore, forcing the outgoing and return current paths apart creates a large "loop area" enclosed by the current loop. This large loop area defines an antenna, which can radiate and/or pick up energy. If the loop area is within a critical size for the frequency of any energy in the loop, a significant amount of energy may be radiated from this virtual antenna, creating EMI/RFI problems.
As if the radiation problem were not enough, the point where the outgoing and return current paths diverge from one another creates an impedance discontinuity, which leads to the very real possibility of sufficient signal reflections that can cause signal integrity problems.
The key to minimizing EMI/RFI problems is to maintain a constant, controlled impedance of all signal transmission lines. Furthermore, maintaining a constant, controlled impedance of signal transmission lines is also important to maintaining signal integrity.
Maintaining this constant, controlled impedance is very important whenever the length of the line is greater than about an inch for every nanosecond of 10% to 90% signal rise time. So, for a signal rise time of 2 ns, a line greater than 2 inches in length must be considered to be a transmission line, have a constant, controlled impedance, and be driven with a source impedance that is equal to the line impedance.
The loss of signal integrity can lead to a number of problems, including but not limited to, jitter or phase noise, crosstalk, improper triggering (including multiple triggering and lack of triggering), and even a complete breakdown in communications.
To say that maintaining a constant, controlled impedance is key to minimizing EMI/RFI and to the maintenance of signal integrity is a simple statement, but just what does it imply?
Remember that current always returns to its source and that the flow of current will follow the path of least impedance. If another signal line provides the lowest impedance path, much of the return current will be within that other signal line, leading to crosstalk between the two lines, a signal integrity issue. The implication here is that traces should be more widely separated than the distance between board layers.
A properly designed power distribution system will have a low impedance to maintain voltage stability. The result is that return signal currents may sometimes use the power plane(s) for the return path rather than using the ground plane. There are a few things we can do to encourage the return currents to flow in the ground plane and to allow return currents to flow in the power planes without problems.
The ground rules
The first rule is to avoid splitting the ground plane. That is, use a unified, solid ground plane with no traces within that plane. This goes against much conventional wisdom, but "we've always done it that way" does not mean that it is the best way. To have vias or throughholes go through the ground plane, however, is O.K. The use of ground planes in more than one board layer is acceptable, but each of these ground layers should be solid with no splits and should be "stitched' to all other ground layers at intervals that are small compared with the shortest energy wavelength in the board. These intervals may not be easily determined, but we have found that stitching with throughholes on a grid of one cm to one inch is generally satisfactory.
If there is at least one ground layer adjacent to each signal layer, the return currents will tend to flow in the ground layer. Because the ground layer is a solid one with no breaks or cuts, the return currents flowing in it are allowed to closely follow the outgoing path, minimizing EMI/RFI problems and quite possibly eliminating the need for bulky, costly shielding.
Furthermore, separating analog and digital areas of the board is very important. These areas are defined by the location of the analog and digital power planes and all signals and components should be completely within their respective analog and digital areas. This correctly implies a split power plane, separating analog and digital power plane areas. However, while there should generally be no reason for signals to cross the analog/digital boundary, when there is more than one digital supply voltage on the board, there will be more than one digital power plane/area and it is sometimes necessary that signals cross this boundary.
As long as the ground plane is adjacent to the signal layer where these lines cross supply boundaries there is no problem as the return current path is confined to the area above or below the outgoing path. However, when no ground plane is next to a signal layer, the return current will find another path. If that path is a signal line in the same or another signal layer, crosstalk is a problem. But most often there is at least an adjacent power plane. Return current flowing in the power plane creates no problem if the signal lines all remain entirely over a single supply plane and does not cross a supply plane boundary or split. The return current will flow entirely within that power plane and remain above or below the outgoing current path.
However, if the signal line(s) must cross a power plane boundary, the return current must find a path around that boundary, creating a large (radiating) loop area, as shown in Figure 1.
Additionally, this diversion of current means a higher impedance path for the diverted portion of the current, creating an impedance discontinuity and the resultant possibility of signal integrity problems. This is most often a problem with 2- to 4-layer boards.
It becomes painfully obvious that two-layer boards should generally be avoided. With a 4-layer board, however, the two inside layers are generally power and ground and the outside layers are signal layers. The problem is with those signals on the side of the board closest to the split power planes when the return currents for those signals want to flow across the power plane boundaries. Because the currents can not flow across the boundary, they flow around that boundary, with the attendant problems mentioned above.
One way to remedy this is to provide two capacitors for the return current path, as shown in Figure 2
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We find that this is sometimes not necessary because there may be a short return current path that we do not see. So, it is generally good to lay out your board for use of these capacitors, then test for differences in radiation and signal integrity with and without these capacitors in place.
The reason for not using a single capacitor between the two power planes is to minimize the possibility of coupling digital noise between the power planes. Providing ground between these two capacitors helps maintain noise isolation between supplies.
1) Use a solid, unified ground plane. Do not split the ground plane.
2) Split the power plane, keeping all power planes in the same board layer. There should be separate power planes for the analog circuitry and for each digital voltage.
3) Use analog power for the ADC digital core supply, but NOT for the ADC digital output drivers.
4) The power for the ADC digital output drivers may be the same supply as for the component(s) driven by the ADC outputs.
5) Locate all analog components and lines over the analog power plane and all digital components and lines over their respective digital power plane.
6) Use separate power sources for each plane. It is generally best to use a linear voltage regulator for the ADC analog power source because analog and mixed signal devices do not behave well with the high frequency supply noise produced by switching supplies.
7) If any digital circuitry is powered by the same supply as the ADC output drivers and has signal lines going to another digital area of the board, use capacitors between the each power plane and ground. Locate these capacitors very close to the signal lines.
While the example used here is of a high speed ADC, it is important to note that even lower-speed converters can be affected by these because digital circuitry today, even with low toggle rates, tends to have very fast edge rates (rise and fall times). It is these fast edge rates that require attention to signal integrity and radiation issues, not just the toggle rate.
