Software Defined Radio (SDR) addresses the tremendous capital expenditure demands placed on operators as wireless standards continue to evolve and change. The cost to install infrastructure is considerable, and it's this cost that inhibits rapid adoption and deployment of new wireless technologies. This poses a significant hindrance to the agility of operators in offering new and improved services to their subscribers.
Paradoxically, the goal of a fully reconfigurable radio that can adapt to a new standard or accommodate multiple standards simply through software upgrades is not limited by software. Indeed, it is the analog domain and its bridge to the digital world that presents system designers with their biggest challenge. The focus of this article is on the challenges of analog-to-digital (A/D) conversion as they pertain to SDR implementations, and how breakthroughs in analog-to-digital converters (ADCs) can bring true SDR closer to reality.
The problem
The big promise of SDR for operators is that it will eventually allow them to deploy one network, and one set of infrastructure capable of handling a broad range of radio frequencies and standards, along with their future evolutions. This requires the radio design to be flexible enough to allow for wider frequency coverage than usual. Additionally, it has to offer dynamic range beyond the range necessary for narrow band applications. So, ultimately, we could deal with a multi-carrier environment with carriers of different modulation types and bandwidths, blocking requirements, and other attributes.
Advances in digital signal processing (DSP) technology have elevated the digital backend capabilities of radios to levels that can be amenable to SDR implementations. Hence, the missing piece of the puzzle is getting the extremely-sensitive analog signals converted to the comfort of the digital domain. A/D conversion in these radios is pivotally important in trying to realize the goal. ADCs are used in both the receiver (Rx) and the transmitter (Tx) sections of the radio, and are the enabling components for SDR development
Key ADC specifications
Among the primary specifications driving the design of the Rx section of the radio are sensitivity and usable bandwidth. In simple terms, sensitivity refers to the radio's ability to effectively process very low-level signals at the antenna input, expressed in dBm. For the ADC, this most commonly translates into signal-to-noise ratio (SNR) specifications expressed in dBc or dBFS (dBc is the ratio of signal to noise expressed in reference to the carrier, whereas dBFS refers back to the full scale input of the ADC).
Closely related to the radio's capability to receive small signals and reject larger interferers is the spurious-free dynamic range (SFDR) of the ADC. This is the ratio of the wanted signal (carrier) to the next highest spurious component in the ADC's output, whether it is harmonic or not, expressed in dBc. Finally, the usable bandwidth of the converter, a term really not specified effectively, deals with the actual signal bandwidth that the ADC can digitize with adequate SNR and SFDR performance.
In standard industry practice, ADCs are specified to their -3dB point of their analog input 'frequency response.' However, a lot of modern day converters show dramatically decreased performance as the analog input frequency increases past 200-300 MHz, even though their bandwidth is rated to several hundreds of MHz.
It's all about bandwidth
One of the key advantages of SDR is its ability to handle a larger-than-usual frequency range without the need for new hardware. This is particularly appealing, given the nature of today's frequency map across the world. Each wireless standard has multiple frequencies defined for operation. For example, GSM alone can operate at frequencies around 400 MHz, 850 MHz, 900 MHz, 1800 MHz, 1900 MHz, and even 2500-2690 MHz for the GSM extension band. 3GPP frequencies include 1800 MHz, 1900 MHz and 2100 MHz, while WiMAX frequencies exist in the 2500 MHz, 3500 MHz, and all the way to 5 GHz, with more coming.
With such a plethora of frequencies, digitizing as large a signal bandwidth as possible through the ADC becomes a huge advantage. Therefore, it is the ADC sample rate that becomes critical in such implementations. The Nyquist criterion limits the bandwidth an ADC can effectively digitize without aliasing (a process whereby the wanted signal after digitization folds over on itself thus producing distortion) to half its sample rate (Fs/2). Thus, for an ADC sampling at 200 MSPS (megasamples per second), the maximum bandwidth that can be effectively digitized is 100 MHz. In practical implementations, though, the filter used to band-limit the analog input to Fs/2 has a finite roll-off, which effectively further reduces the usable bandwidth.
Beyond the receiver, the demand for high bandwidth also is key for the transmit section of the radio. Since the cost of the power amplifier is proportional to its output power, a key method of reducing the overall bill-of-materials (BOM) and operational cost is through increasing its efficiency. Modern digital pre-distortion algorithms that linearize the power amplifier at the transmitter rely on feeding back to the digital processor a digitized bandwidth that is a multiple of the transmitted signal's bandwidth. This, in turn, necessitates the use of an ADC capable of sampling at very high rates.
Signal-to-noise ratio
In order to maintain utmost sensitivity, an SDR design has to feature a large SNR so that very low-level received signals can be discerned, and effectively demodulated. The evolution of wireless standards to higher-order modulation schemes (such as 64QAM) imposes more stringent requirements on the SNR performance of the ADC. In situations where the received input power at the antenna is really low, the SNR of the ADC (in conjunction with the phase noise of the local oscillator) becomes the limiting factor and sets the sensitivity for the entire receiver.
Until recently, SDR designers had to trade off SNR for sample rate (bandwidth), since the state-of-the-art ADCs at several hundred MSPS were limited to resolution of 10 bits, with SNR levels around 50 dBFS. With the introduction of converters such as the ADS5463 (12-bit/500 MSPS), the envelope for monolithic 12-bit, ADCs essentially has doubled (previous art was at 250 MSPS). With SNR levels jumping to the mid-60s, implementations previously prohibitive can now become reality.
In addition to being able to effectively reconstruct as large an analog signal bandwidth as possible, the sample rate of the ADC offers an added benefit, usually referred to as processing gain. Typically, SNR for an ADC is calculated as the ratio of the power of the fundamental of a sinusoidal tone to the sum of the noise across the entire Nyquist band of the ADC (0 Hz through Fs/2, excluding DC). Typically, total noise is uniformly spread across the Nyquist zone. When the receiver processes a signal of a certain bandwidth within that zone, powerful digital filters can greatly attenuate the out-of-band noise. When the signal of interest has a bandwidth BWSIG and the ADC samples at a rate of Fs, the effective processing gain (PG) can be calculated as:
Figure 1 shows the processing gain that can be achieved by using a very high-speed ADC such as the ADS5463, sampling at 500 MSPS.
Figure 1: Processing gain versus wanted signal bandwidth for an ADC sampling at Fs = 500 MSPS
(Click to enlarge image)
The power of the digital backend of the SDR can fully exploit the benefits of the wideband capabilities of the ADC.
Ultimately, the evolution of wireless receivers will entail direct sampling at the RF frequency. Although the ADC technology needed for such a task is not feasible today, it is not unreasonable to expect that eventually technological breakthroughs may enable it.
However, jitter needs to be taken into account since, ultimately, it will limit the SNR. The well-documented equation that relates SNR to jitter for a sampled system is given in Equation 2:
where fin represents the analog input frequency, and tjitter the RMS value of the system's jitter. The internal jitter of the ADC sampling circuitry is added (in a root of the sum of squares fashion) to the externally provided sampling clock to the ADC.
Note that the limitation of SNR is independent of the actual sampling frequency, but directly related to the analog input frequency. This fundamental limitation is a major design consideration when deciding the placement of the intermediate frequency (IF) in receiver design. The benefit of simplified Rx architecture and filtering (and, hence, reduced cost) is countered by the limitations imposed by jitter and clocking the ADC as the IF is increased.
Spurious-free dynamic range (SFDR)
The linearity of an ADC, most often characterized by its SFDR, becomes critical in situations where the incident power at the receiver's antenna is of substantial power levels. This can happen when the wanted signal is strong (a desirable situation), or when an in-band interferer is strong (an undesirable situation).
In the latter case, the linearity of the ADC dictates whether the wanted signal can be effectively demodulated. This is particularly true when the desired signal's power is low. The presence of a large interferer effectively limits the application of any AGC function, since the total signal (wanted plus interferer) may already be approaching the full-scale range of the analog input. Thus, the ADC's inherent linearity performance becomes the bottleneck.
Just as jitter limits how high an SDR designer can place the IF, SFDR also weighs into that decision quite heavily. Many ADCs available in the market today exhibit high levels of linearity that are, however, limited to input frequencies below 200 MHz. Hence, the benefits of high IF placement cannot be realized due to the roll-off in SFDR performance.
New analog structures using cutting-edge BiCMOS process technologies have enabled the inclusion of an analog input buffer, capable of delivering high levels of SFDR across many hundreds of MHz. The analog input buffer of the ADS5463, for example, allows the user to easily achieve datasheet performance because it isolates the sensitive analog input from the switching within the ADC.
Additionally, it provides constant impedance across input frequency. Figure 2 shows that a converter such as the ADS5463 enables SFDR performance of over 70 dBc, for IFs at least as high as 500 MHz.
Figure 1: ADS5463 SNR and SFDR performance over analog input frequency at 500 MSPS
(Click to enlarge image)
This dramatic improvement in performance substantially simplifies the design of the radio, especially since it is coupled with very high levels of SNR and processing gain. Using a very-high input frequency can further reduce the cost of the radio, since it removes an extra down-conversion step and its associated BOM impact.
Conclusion
The promise of true software-defined radio depends heavily on the evolution of high speed A/D conversion. Located at the heart of both the receiver and the transmitter, the ADC sets the performance for the entire radio. Recent breakthroughs in mixed-signal technology have enabled performance at unprecedented sample rates and analog input frequencies, simplifying the radio design and allowing for broader operating bandwidths and higher levels of sensitivity. As ADC technology keeps pushing the envelope, it will continue to pave the way for the advent of truly reconfigurable, multi-standard radio.
About the Author
Yiannis Papantonopoulos is Systems and Applications manager for high-speed ADCs at Texas Instruments Inc. He can be reached at yiannis@ti.com.
