(You can read Part 1 of this article by clicking here)
PWM Comparator
Another application of auto-zeroing comparators is in the main control loop of a PWM system. The comparator in this application looks at the difference between a reference level and the output of the loop error amplifier. Figure 4 shows a simplified schematic of a PWM control loop.
Figure 4: PWM control loop
(Click on image to enlarge)
Most comparators will have a systematic offset that can be minimized by keeping the comparator gain high; however, offsets can be introduced during the layout phase of the comparator design. While these offsets are cancelled out for the most part in the closed-loop system, comparator offsets can become important when the duty cycle of the system becomes very small.
Portable electronics systems, such as laptop computers, increasingly fall into this category of PWM systems due to the fact that the battery-charger output voltage is typically around 20 V, while the regulated supply voltages on the memory chips and processors needs to be around 1 V. This set of voltages will create a duty cycle of VOUT/VIN equal to 1/20 or 5%.
Under this condition, the comparator will be working at the bottom of the PWM ramp, where the slope of the ramp is smallest and the pulse width to be processed out of the comparator will be very narrow. If the system clock is running at 600 kHz, the comparator must then be able to support a pulse width of 1.67 μs/20 or about 83 ns. This situation is depicted in Figure 5.
Figure 5: PWM timing
(Click on image to enlarge)
Any offset in the comparator that causes that number to become smaller can create instability in the control loop and force the system to compensate by alternating wide pulses and narrow pulses in order to maintain the duty cycle. This shows up as pulse jitter and will cause a larger ripple voltage at the output of the converter. In its most severe case, the comparator might miss a pulse cycle altogether causing a subharmonic condition.
With the auto-zeroing comparator, the system can be in the offset-sampling mode during the time that the PWM ramp is at the bottom of the ramp, and then switched to the input-sampling mode at the start of the ramp. The auto-zeroing comparator system can detect millivolt differences and thus be able to maintain very small pulse widths in very low duty-cycle PWM systems.
Figure 6 shows a simulation of a PWM system using a conventional CMOS-comparator design.
Figure 6: Offset of CMOS comparator in PWM system ˜ 22 mV
(Click on image to enlarge)
The simulation shows the difference between the crossing levels of the ramp at the input to the PWM comparator versus the actual error voltage at the input to the comparator. The difference between the two is the comparator offset. In the case of Figure 6 the offset is around 25 mV. This offset will limit the range of usable ramp for a stable system at very low duty cycles.
Variations in the slope in the ramp will also contribute to the loop offset. In systems designed to operate from a battery, most PWM controllers will include a "feed forward" path from the battery that will sense the battery voltage and adjust the slope of the ramp compensation in order to keep the system stable. If the PWM comparator has additional offsets, then as the battery voltage changes, the system can experience regions of instability which show up as jitter or alternating wide and narrow width PWM pulses.
In Figure 7, the auto-zeroing comparator has significantly less systematic offset and therefore allows the system to behave with better stability throughout the range of duty cycles.
Figure 7: Auto-zeroing comparator offset ˜ 8 mV
(Click on image to enlarge)
With the emphasis on highly efficient portable electronics with longer battery life, system designers must be aware of all the techniques that can be used to improve both the efficiency and accuracy of the system voltages that supply the circuits in those systems. The use of the auto-zeroing comparator to extend the operating range of PWM control systems is one more tool in the designer's kit of techniques to improve the accuracy and performance of PWM systems.
About the author
Stephen W. Bryson is a Principal Design Engineer at Fairchild Semiconductor Corp. San Jose, CA. He has published several papers and has patents in the area of power management and drivers. He has a BSEE degree from Oregon State University and a MSEE from Santa Clara University.
