I hope you'll take a moment to respond to the visitor poll on the Planet Analog home page. I'm chairing a panel on top-down Mixed-Signal Design at HDLcon later this week (March 2nd at the Santa Clara Marriott) and your experiences with mixed-signal design should make for an interesting discussion.
I've written a number of times that there is little consistency about the meaning of mixed-signal design, and that IC, ASIC and EDA tool vendors will use the term to cover a multitude of sins. I won't argue whether Cirrus Logic's ARM-based MP3 audio decoder should be called "mixed-signal," even though it's implemented in digital CMOS and spends all of its clock cycles slamming around ones-and-zeros. But that is a totally different mixed-signal device than, say, Analog Devices' Microverter which pairs a 12-bit A/D converter with an 8051 on the same chip. And different again from the Maxim RF ICs which use silicon germanium (SiGe) on CMOS substrates. In each case, the meaning of "mixed-signal" design represents an entirely different set of problems for the engineer - and a different set of hoops for the EDA tool vendors to jump through.
Friday's panel was assembled by that extremely savvy EDA industry press agent, Georgia Marszalek. If there is a cohort that is really knowledgeable about the impact of tools on mixed-signal IC design, these are some of its superstars: John Wright of American Micro Systems (AMI), Ian Wilson of Antrim (who also serves as chairman of Accellera's Analog, Mixed-Signal Technical Committee), Kevin Cameron of National Semiconductor, Gary Pratt of Mentor Graphics, Jon Sanders of Cadence, Avant!'s Doug Lundin (you may remember him from Analogy), Rajit Chandra of Magma's Moscape subsidiary, and the always acerbic Rob Rutenbar of Carnegie-Mellon University.
At the Design Automation Conference (DAC) last year, Rob Rutenbar cracked everyone up with comments about Microsoft's commitment to op amp design, and EDA tool partnerships that are frustrating and endearing at the same time. (The image of pain-and-suffering on my home page is from his presentation this week.) He nonetheless made points for the EDA industry last June by showing how - frustrating and painful as it sometimes can be -the use of mixed-signal tools saves time-to-market. Count on him to do the same here.
I happily used John Wright as the spokesperson for analog EDA issues at last September's webcast of the Analog and Mixed-Signal Applications Conference. At HDLcon this week, I expect John to identify some of the choke points in the mixed-signal design flow. National's Kevin Cameron says he's been looking (all his life it seems) for analog-and-digital simulators to play well together, and he believes hardware description languages (HDLs) can help, but after that it starts to get fuzzy.
All of the EDA tool vendors on my panel acknowledge that some combination of bottom-up and top-down design will have to do for mixed-signal design, that models and model libraries count (that building accurate, meaningful models is no mean fete), but that the usefulness of top-down HDL-driven approaches will depend on precisely what we mean by mixed-signal design.
Are we talking about mixed-level design, in which designers are trying to pair individual gates to cells (or transistors to gates)? asks Avanti's Doug Lundin. Are we talking about mixed technology, in which bipolar driver transistors (SiGe, for example) are implanted on a CMOS substrate? Are we talking about mixed analog-digital technology, in which some part of an SOC must interface a variable voltage? Or are we simply worried about noise and parasitics in (call-it-what-you-will) an all-digital circuit? In EDA realms, everybody likes to talk about mixed-signal design tools and mixed-signal design flows for ICs and SOCs, but - until we have definitive answers to these questions - nobody has a precise idea what this means.
Among the 1000 engineers I surveyed in 1992 for an Indian Forest Research project on mixed-signal design tool use, less than 1% identified their work as exclusively analog. Thus, the real analog artists - guys like National's Bob Pease or Linear Technology Corp.'s Bob Dobkin - are (and will always be) a distinct minority. While the design tool vendors openly acknowledge there is a much larger market potential addressing the digital guys with SOME kind of analog design responsibility, nobody has a clean fix on what that analog responsibility really is. In that 1992 study, everyone used some form of Spice. Most were INTRIGUED by the use of hardware description languages, but not yet COMMITTED. Here it is, nine years later, and I'm curious if we know more now than we did then.
To an outsider, the EDA tools market (and the related IP market) looks very unfocused. There are dozens of interesting point solutions that are supposed to be incorporated into something that feels like a consistent "design flow." Yet, even the toolsets marketed by the largest tool vendors - Cadence, Mentor Graphics, Synopsys, Avanti - can often feel like so much "work in progress" (i.e., loosely connected, incomplete, sometimes buggy). Thus, every big chip you build STILL feels like a crapshoot. Doesn't matter how many analysis tools you've incorporated into your so-called design flow, it still feels like the proverbial blind men using their hands to characterize an elephant. It doesn't matter that the sign-off sheet for first silicon might require 160 signatures: it's still a gamble, and - heart in your mouth -you know it.
For mixed-signal design, the guys on my panel might be in some position to help. But they'll obviously need some kind of input from you.
