With each company trying to outdo and outspend the next at restaurants and dance parties, the Design Automation Conference (DAC) is always a lot of fun. This year DAC shared the enormous sprawling Los Angeles Convention Center with some kind of erotica convention. But the Lakers' early playoff victories brought another zillion hooting yellow-shirted fans and dozens of tailgate parties into the area, adding some life to the otherwise bleak nothing-ever-happens-here terrain of downtown Los Angeles.
Despite my previous conjecture ("Who loves ya, baby"), analog remains the bastard child of the EDA industry. It accounts for about $200 million in revenues in an industry, which, in a bad year, churns out about $2.5 billion in license fees, according to Dataquest. So you always need to hunt for analog developments at DAC, and this year's was no different.
I saw two trends, opposite poles of a continuum stretching from grand sweeping tools that might revolutionize design flows on one side, to useful almost mundane design aids that speak to an analog sensibility on the other. For instance, Neo Linear (Pittsburgh) was tooting the horn for analog synthesis. It is developing a software product that will accept specifications, an unsized schematic and process rules, and - using the designers' own simulator and design environment - will generate a sized netlist that can be fed to a cell generator or layout editor. The NeoCircuit tool, which Neo Linear hopes to formally introduce before the end of the year, can be used for four things, according to engineering vice president Anthony Gadient: It can be used to (1) design a new circuit, (2) explore circuit alternatives, (3) migrate a circuit to a new process, or (4) retarget an existing circuit.
Those who've seen this tool, like Dataquest's EDA analyst Gary Smith, believe it most likely will be used for process retargeting - an operation he prefers to call "target compiling" (rather than "synthesis"). The problem, of course, is that certain types of circuits won't scale properly in the retargeting process. In CMOS, for example, the noise floor (all those clicking switches) rises as geometry shrinks. You'll reach a point where the only way to keep a signal above the noise floor is to redesign the circuit (i.e., redraw the schematic). "If the tool can't find an optimized netlist that meets the spec - and noise is part of the spec - it'll tell you," insisted Ron Rohrer, Neo Linear's chairman.
Of course, analog synthesis is on the radar for Synopsys, the company that pioneered logic synthesis, building on successful research performed in the late 1970s and early 1980s by Art deGeus at Research Triangle Park. At the Wednesday dinner he hosted, deGeus, chairman and CEO of Synopsys, reminded us of the Erotica LA show and jested it might merge with DAC next year. He was in obviously better spirits that night than he was on Monday after hearing Vinod Menon's biting comments at the EDA Consortium's (EDAC) awards luncheon.
Menon's team at Advanced Micro Devices received the EDAC association's silver award for the design of a multiport Ethernet controller, a complex mixed-signal system-on-chip (SoC). But in his acceptance speech Menon told the luncheon gathering, "We used practically every EDA tool available and pushed the envelope on every tool. In fact I am proud to say that we broke every one of them."
"We have great respect for people who have broken our tools," deGeus, who serves as EDAC vice chair, said afterward, but he was obviously stung. His words would have seemed very gracious if Menon hadn't continued to rag on the EDA industry. "You need to make sure the software tools are in the same league as the products we produce," Menon criticized. Definitely a bite-the-hand-that-feeds-you-lunch kind of speech.
In an interview with EE Times' Margaret Quan after the awards ceremony, Menon claimed that bugs in the tool sets hampered the efforts of his design team. He said his team encountered "phantom errors and artifacts from the tools," and there was "coupling between signals that the tools could not detect" - an analog problem.
"The tools could not handle the size of the design," was Menon's biggest complaint. "This cut away from our productivity because we were chasing artifacts on tools vs. problems on our design." The four major EDA tool vendors - Avant!, Cadence Design Systems, Mentor Graphics and Synopsys - "have a long way to go," he said.
Why does this sound familiar?
I remember Mely Chen-chi of Taiwan's Industrial Technology Research Institute complaining about the lack of service support Taiwan manufacturers were getting from American EDA tool vendors at an EDA business forum I chaired in Hsinchu one summer. It takes several days to turn around a phone call or e-mail request, she said, and there is typically no one available in Taiwan to provide on-site help with a pressing EDA software problem. If American FAEs venture west from California, Chen said, they only get as far as Japan.
Bill Fuchs, then president of a company called Simucad and chairman of the Open Verilog International consortium, was sitting with me during Chen's talk. "She's damned right!" he turned to me then, "the EDA industry treats EVERYONE like dirt."
And Felicia James, a mixed-signal IC designer at Texas Instruments, was so riled at the EDA industry that I was afraid I'd have to gag her at a DAC panel I chaired years ago in Las Vegas (or was it San Francisco?). She was incensed that she had to spend time writing patches for the EDA tools just to get them to perform as advertised. Robert Dobkin, Linear Technology's founder and chief technology officer (the inventor of the three-terminal linear regulator) sat on this panel. Never a great fan of EDA tools, he was willing nonetheless to give the tools audience the benefit of the doubt. "How do you simulate 24-bit precision?" he threw out, rhetorically.
This year's panel (a lot of fun, by the way) was not very different. Between the academics and the EDA industry representatives, Rudy Koch, a mixed-signal and RF design chief at Infineon Technologies in Munich, played the voice of reason. He described the interaction of CAD tool experts and semiconductor designers as a "clash of civilizations."
Koch got laughs and applause when he said, "CAD engineers have never designed a chip, concentrate on digital because it is easier to understand than analog and check their tools only with inverters and latches (anything else is too complex)," he joked. "Analog designers, on the other hand, are proud of their 'craftsmanship' and feel insulted when a tool can handle what they have learned the hard way. RF designers are like analog designers, but even more so. Though they never use more then three transistors in a block, their language cannot be understood by anybody else."
Some of the problems posed by new-generation mixed-signal SoCs are fairly well known to mixed-signal IC designers, Koch said. These include topology generation and selection, circuit sizing, selective analog back annotation, device modeling (especially for inductors) and mixed analog digital cosimulation. Some of the newer concerns include analog place-and-route, specialized simulations (to visualize the effects of noise, crosstalk, power lines, substrate coupling, wire bonds and packages) and the mixture of design flows - not just analog, digital and RF, but also top-down and bottom-up design styles.
Yet, as much as the semiconductor people will portray EDA software tools as nave, buggy and unpolished, it seems to me they can't do anything without them: the ICs are just too complex to do anything by hand (or intuition) anymore. Granted, first silicon signoff is always something of a crap shoot, but the semiconductor folks will run every tool, do every check they can think of, just to get there.
For every problem that Koch named, I know a tool in development trying to address it. Topology generation and selection, and automatic circuit sizing is what Neo Linear is working on. Worried about device modeling? Look at some of the newer AMS model-building tools from Cadence and Mentor. Need specialized simulations? Look at Ansoft's HFSS lead frame analysis tools or Snaketech's or Cadmos' substrate analyzers. Considering mixed-signal design flows? Talk to Antrim. These people don't have five years and the code debugging resources of a Microsoft. There aren't armies of people working on this stuff, just small teams of dedicated people trying to make themselves useful to the engineering community.
But it was an academic, Rob Rutenbar of Carnegie Mellon University, who turned out to be the best spokesperson for the EDA industry, describing how university-originated tools took three months off the design time for a Texas Instruments network interface IC - indeed, the same kind of part for which AMD won an EDAC award.
Always entertaining, Rutenbar flashed a copy of Microsoft's OpAmp 2000, a Windows-based design kit for op amp designers. He said that his nondisclosure agreement with Microsoft forbade him from talking about it, but that he was able to verify that it was a significant improvement over OpAmp 98.
Rutenbar told another joke that may console the battle weary EDA tool vendor: A semiconductor designer and a CAD tool vendor are awaiting execution before a firing squad. The executioner enters and says: "Do you have any last requests?"
"If I had my druthers," the semiconductor designer stands up, turns to the CAD advocate and, in a voice dripping with the same kind of passionate scorn and venom one might reserve for a jilting lover, says, "I'd tell you what I think of your impossible visions, your buggy software, your clunky test tools and your ridiculous license fees."
"Do YOU have any requests?" the executioner asks to the CAD vendor.
"Yeah," he says. "Shoot me first."
