NeoCell uses algorithmic intelligence to generate compound cell topologies from a small set of module generators. The system prioritizes device geometries and performance among the constraints it uses to build an analog cell. It calculates the parasitic capacitance and resistance from the chosen device and routing patterns, and it optimizes the design to maximize performance and minimize the parasitics that result from mismatch.

Neo Linear says it crafted NeoCell-the first product in a planned family of mixed-signal integrated design tools-for seamless integration into existing design flows and compatibility with industry standards.

"Analog-cell physical design is still mostly a manual-labor-intensive process," said company president Charles Buenzli. The analog content of a typical mixed-signal IC accounts for only 10 percent to 20 percent of the die area but 50 percent to 70 percent of the total design effort, creating a bottleneck in the development process.

The scarcity of experienced analog designers compounds this problem," said Buenzli. Thus, ease of use was a key consideration in crafting NeoCell.

Neo Linear's work builds on analog-synthesis research conducted by Rob Rutenbar at Carnegie-Mellon University. Rutenbar's experimental analog-synthesis systems functioned like early-generation silicon-compilation systems. Instead of actually synthesizing an analog circuit from scratch, the synthesis tools would analyze the requirements of the design and then search for cells-in a pre-existing cell library-that might meet the requirements of that design.

The chances of making such a process competitive with hand-crafting are contingent on a fast, complex search engine and a massive library of analog cells. The NeoCell tool proposes to automate the construction of those cells.

That is not an easy task. Unlike logic circuits, which represent logic 1s and 0s and have fairly consistent geometries, analog circuits are scaled according to the voltages and currents they must produce. Relative to digital logic, an amplifier circuit, for example, uses only a small number of transistors. But those transistors can reflect several geometries and even multiple technologies. The optimum choices of geometry and technology for any particular circuit could more easily made by an analog expert-a human operator-than by computer. But knowledgeable analog experts, Buenzli noted, are increasingly hard to find.

Before NeoCell, certain layout techniques that are well-understood by analog designers were not incorporated into automatic cell generators. Those techniques include device merging and abutment (in which, say, a string of bipolar npn transistors share a common base), symmetrical placement (for matching push-pull circuits) and the placement of transistors to create a thermal gradient across a chip.

Done by machine, analog layouts would exhibit poor density and performance. Buenzli believes NeoCell can produce analog layouts that are competitive with hand-crafting.

The NeoCell layout system has four parts, which are generally used in sequence. First, layout constraints and user preferences are added to the cell's schematic using the NeoCell Constraint Editor. "It's just like a designer would instruct a layout engineer," said Buenzli.

In the second step, the designer uses the Cell Architecture Editor to define such parameters as the boundaries of the cell, the intracell pin locations and the power and ground rails. NeoCell annotates the cell's Spice net-list with the cell architecture and layout constraints and then passes the net-list to the place-and-route engine. The designer may also create the annotated Spice net-list with a text editor. An intelligent placement editor and a router are provided as well.

In the third step of the cell-design process, the NeoCell auto-placer creates a number of alternative layouts that can be edited interactively in the NeoCell device-level layout editor. During interactive editing, NeoCell automatically satisfies all of the hard constraints and design rules. Consequently, if the designer moves one device of a symmetric pair, its paired device is automatically moved to preserve the symmetry constraint.

In the fourth step, the designer routes the layout either automatically or interactively. For example, he can route critical signal nets interactively and then route the remaining nets automatically with a final interactive touch-up pass. The completed layout is then exported as GDII into an existing polygon-level editor or cell-assembly tool.

The first release of NeoCell is integrated with Cadence Design Systems' Composer schematic-capture tool and Virtuoso polygon-level editor. NeoCell is available on Sun systems running Solaris version 2.5.1 or later.

NeoCell is being demonstrated in the Neo Linear/Trust Computer booth number 133 in Hall A2 at Electronica 98.