DDR memory has emerged as the leading technology for in-system DRAM. Verification of DDR systems has also emerged as one of the most challenging and time consuming tasks of modern digital system design. Logic analyzers are key in assisting engineers with the verification of these systems. However, with the cost and spatial constraints being imposed on designers, logic analyzer probing is becoming a concern.

In an ideal world, DDR testability would be part of the final design. This would allow test-bench verification of the system as cost engineering and outsourcing occurs over the life of the product. However, this has not been practical until today due to electrical loading and space requirements of logic analyzer probe points. New connectorless logic analyzer probing is allowing DDR testability to be incorporated into the initial and final stages of a product with little impact on cost, board space, or signal integrity.

The first consideration is spatial. Designers do not have an infinite amount of PCB space available. Thus, the memory system must be implemented in as little space as possible.

A second important constraint is cost. The main impact of cost is in the reduction of layers on the target PCB. Many DDR systems are being implemented on 4-layer PCB's that have only two signal layers. While DDR sockets are pinned out for this style of routing, it is challenging to accommodate miscellaneous circuitry that is also needed by the DDR system.

Another problem faced by designers is signal integrity. The sheer number of signals and high data rates, make a DDR system a very difficult implementation. When adding the additional constraint that there are only two routing layers and that the system must be as small as possible, designs are continually running out of margin.

A final but important consideration is testability. With all of the above constraints on designers, there is usually little space or margin in the system to incorporate testability. However, testability is key to the validation and time-to-market for the product. To exacerbate this situation, designs are often changed or cost engineered during the life of the product. When a product is changed in production, there needs to be a quick and reliable method to validate that the changes have not altered the original functionality of the design. Until now, leaving testability in the production design was not an option due to electrical loading and the space/routing required. However, with connectorless logic analyzer probing all that has changed.

The following figure shows an example layout of a DDR system using four Socketed, 184-pin DIMMs. This system is double terminated with the connectorless probes placed between the terminations (midbus probing). This figure is showing the topside routing for all 2x signals (data and stbs). The 1x signals (address and control) are routed in a similar fashion on the bottomside of the board. Each SoftTouch footprint contains 34 channels of testability. It takes three footprints to test the 2x data in the DDR system. The bottomside of the PCB contains two SoftTouch footprints to test all of the 1x DDR signals. To understand the power of the connectorless probes, the incremental impact on the system should be explored.

Figure 1:  Example layout for SoftTouch probing of a DDR system (Showing only Topside 2x Data)

Another exciting benefit of the connectorless probes is the flow through routing capability. The footprint and pinout of the logic analyzer probe is such that signals can traverse the testpoints without having to change layers. This means that in a DDR system, no additional layers are needed to incorporate logic analyzer testability. This is crucial to a system implemented on a four-layer board.

A typical four-layer DDR system uses 0.005-inch trace widths routed on the outer layers of the PCB. These layers are designed to be 50 Ohms. For this type of microstrip trace, this corresponds to ~3pF/inch of capacitance. To examine how much additional loading is present due to the logic analyzer probes, consider the cases when the probe is connected and when it is not connected.

CASE 1: When the probe is connected
	Additional trace due to testability	= 0.390"
	Parasitic Capacitance of trace	= (0.390") * (3pF/inch) = 1.17pF
	Additional Probe Capacitance	= 0.7pF (NOTE: This includes the pads)
	Total excess capacitance due to testability	= 1.17pF + 0.7pF = 1.87pF

CASE 2: When the probe is NOT connected
	Additional trace due to testability	= 0.390"
	Parasitic capacitance of trace	= (0.390") * (3pF/inch) = 1.17pF
	Additional probe pad capacitance	= 80 fF
	Total excess capacitance due to testability	= 1.17pF + 0.08pF = 1.25pF

To understand if this capacitance is of concern, a first order analysis of the system must be done.

Capacitance of DDR system as seen by driver
	Total trace length of original system	= 2.767" (NOTE: Using longest 2x trace)
	Parasitic capacitance of trace	= (2.767") * (3pF/inch) = 8.3pF
	Lumped capacitance of DIMM	= 5pF (NOTE: DDR333, DQ, DQS, DM)
	Number of DIMMs on bus	= 4
	Capacitance due to DIMMs	= (4) * (5pF) = 20pF
	Total capacitance of DDR System	= 8.3pF + 20pF = 28.3pF

This first order analysis shows that when the probe is connected, it only adds an incremental 6% to the capacitance that the driver sees. Even more importantly is that when the probe is not connected, the testpoints and traces left on the PCB only add an incremental 4%. This means that leaving the connectorless footprints on the final production design will not significantly degrade the signal integrity of the system. The benefit of having testability incorporated into a shipping product is extremely valuable and well worth the 4% margin reduction.