A wide assortment of precision devices is readily available to designers building high-performance systems. For these systems, layout and design is very important. However, for systems with multiple boards, board interconnection can be a critical piece of the printed circuit board (PCB) design. While we might have paid little attention to interconnection details, because we didn't think they would apply to our remote sensing circuit, this is not the case in many situations.
Connecting a relatively "slow" analog/digital converter (ADC) with a 2.25-MHz clock across a short, one-meter wire to the microcontroller is as easy as buying and plugging in the wires. But a poor PCB interconnection design easily can ruin a great design using fabulous parts. But, not our problem--or so we thought!
In this article we'll focus on the critical or what could be seen as "surprise" factors when achieving a high-performance PCB interconnection system.
Figure 1: Physical arrangement of an ADS8326EVM and MSP430F449 boards
connected by a one-meter, twisted-pair communication cable.
(Click on image to enlarge)
Figure 1 shows a one-meter, CAT-5 twisted-pair cable connecting a successive approximation register analog-to-digital converter (SAR ADC) represented by the ADS8326, and a microcontroller represented by the MSP430 evaluation board (EVM). The ADS8326 is a 16-bit, high-speed, 2.7 to 5.5V micropower ADC. The system clock frequency for this device ranges from 24 kHz to 4.8 MHz.
The microcontroller transmits a 2.25 MHz clock and chip select (CS) signal across the CAT-5 cables to the ADC (Figure 2). The ADC responds by transmitting the conversion data back to the microcontroller.
Figure 2: A CAT-5 twisted-pair cable carries the clock and chip select (CS) signals from the microcontroller to the data converter. This same cable completes the SPI interface by carrying the data signal from the ADC back to the microcontroller.
(Click on image to enlarge)
Due to the slow clock rate, termination issues between these two devices were not apparent at first. Surprisingly, we found that transmission data between these boards, combined with the mismatched characteristic impedances, caused significant reflection errors across the one-meter loop. These reflections distorted the clock and data signals between the boards.
Figure 3 shows what happens when line impedances between two boards are overlooked. CH1 shows the 2.25 MHz clock signal transmitted from the microcontroller side of the circuit to the ADC board. The ADC uses this clock signal to synchronize data transmitted back to the microcontroller. CH4 shows the data's arrival from the ADC at the microcontroller.
Figure 3: The microcontroller generates the conversion clock signal (CH1) and sends it to the ADC.
CH4 shows the microcontroller receiving conversion data from the ADC.
(Click on image to enlarge)
Both channels show that signal distortion exceeds high- and low-level thresholds, with significant signal overshoot and undershoot occurring. These signals have false edges or ringing, and reduced operating margins. Looking at the ADC side of the circuit, we see similar effects.
Our immediate response to the ringing reflected in Figure 3 is to slow down the clock's frequency. You may find a quick and successful fix, or you may be challenged as we were in this example. Frequently, engineers are convinced that the clock rate dictates the type of PCB to be implemented, thus ignoring the clock's rise and fall times or switching times. However, in order to tame transmission line effects, define your highest frequency signal based on switching times--not signal frequencies.
Effective Operation Frequency
High-performance interconnect systems require attention to long transmission-line issues, such as reflection and termination. The actual clock frequency describes the clock or data rate in the application. In our test circuit, this frequency is 2.25 MHz. The effective operating frequency (EOF) of a PCB circuit is defined as:
or
where the signal's EOF is equal to the system's EOF, tRISE is equal to the rise time, and tFALL is equal to the signal's fall time. Equation 1 defines the signal's rise and fall times.
For a worst case calculation, use the smaller value between tRISE and tFALL.
When determining the rise time on the bench, be aware of any test equipment limitations. Using an oscilloscope display, calculate the switching signal's rise and fall times and EOF by inspection. For instance, if the measured signal's rise time is 2 nsec, the signal's EOF is 175 MHz.
Equipment errors can be accounted for with a formula that uses the square-root-of-the-sum-of-the-squares or root-sum-square (RSS). For instance, the bandwidth of your probe can be 500 MHz, while the oscilloscope's bandwidth is 350 MHz. Using a RSS formula, the measured rise time of a 2 nsec signal, and the equipment limitations above, are actually equal to 1.6 nsec. Now calculate this using the following formulas:
(Click on equations to enlarge)
Using this calculation, the switching signal is 221 MHz. This is far above the ADC's actual operating clock frequency (2.25 MHz) and the previously calculated EOF of 175 MHz.
Reflections Galore
Now that we have determined the system's EOF, let's characterize the connections between the microcontroller and the ADC by defining the critical length of our transmission line. In our test system, signal rise time, propagation delay and cable length are related.
Propagation delay is the time required for a signal to travel from a driver to a receiver. A major high-speed PCB design challenge is to make sure this delay time is less than the signal's rise or fall time.
If the signal propagation delay time is less than one-seventh of tRISE (<15% x tRISE), we can model the connection as an inductive-capacitive pi model (LC pi model). If tRISE is greater than the propagation delay time, we'll use the microwave theory to model the board interconnection transmission line.
In contrast, if the lines are sufficiently short, the signal will rise during the line's propagation delay, and the reflection becomes part of the rising edge. With longer connection lines, the propagation delay may be greater than the signal's rise time, and reflections appear as an overshoot or undershoot.
Propagation delay time (TPD) is proportional to the relative dielectric constant of the twisted"pair wires (Equation 2 and Reference 1):
For AWG 24 wire, the typical TPD is approximately equal to 134 psec/inch (52.7 psec/cm). As long as a cable length is longer than 1.68 inches (4.27 cm), and the signal switching time is less than 1.6 nsec, the transmission-line model is required to analyze the cable.
In transmission line theory, the voltage and current along a transmission line can vary in magnitude and phase as a function of position. ZO is the characteristic impedance of the transmission line when it is infinitely long or ideally terminated.
The twisted pair cable formula for its characteristic impedance is (Equation 3):
where Er is the relative dielectric constant of the cables.
The wire's insulator and air permittivity determine the value of Er. The distance between the cables is D, and the diameter of the cable wires is a. For an AWG 24-wire, where D is equal to 0.038 inches, a is equal to 0.02 inches, Er is equal to 2.5, and ZO is 101 Ω. The transmission line's characteristic impedance largely influences the transient response of a signal passing through it.
The voltage reflection coefficient (Γ') is the amplitude's ratio of the reflected voltage wave to the incident voltage wave. ZL is the load impedance (Equation 4):
If the load is mismatched to the line, the incident wave will be reflected at the line and load's interface. Consequently, power delivered to the load will be reduced. This is also called return loss or RL.
For our test system, the driver (microcontroller) has an internal source resistance of 20 Ω The cable characteristic impedance (ZO-430) is close to 100 Ω ý and the receiver's input impedance (ADC) is 1 GΩ. The output impedance of the driver (ZO-8326) may change with current demand or vary from device to device. The receiver's input impedance (ZL-8326) may be greater than 1 GΩ. An infinite value for ZL produces a reflection coefficient of one.
A digital rising edge acts like a pure AC signal. When an AC signal reaches the end of the transmission line path with a mismatch between ZO and the termination ZL, a portion (up to 100 percent when reflection =1) of the wave is reflected.
When the wave reflects back along the transmission line it eventually reaches the original source. If a mismatch exists between the ZO and the source impedance (ZS), some portions of the wave are re-reflected again. The superposition of these reflected waves can cause significant signal degradation.
With Figure 4, the reflection factor at the receiver end is one, and the reflection factor at the driver end is -0.8. From these two numbers we can calculate the exact ringing amplitude at any time during the signal's propagation. The initial driver signal is 3.3 V.
Figure 4: Signal being reflected between a microcontroller driver pin and the ADC receiver pin
(Click on image to enlarge)
When a signal transmission is initiated (Figure 4) a 3.3 V signal on the microcontroller's drive side transmits to the ADC. When this signal is initiated voltage at the microcontroller is equal to 2.75 V because -0.8 is the reflection factor at the microcontroller interface. After one propagation delay period or TPD, a 5.5 V signal appears at the ADC interface. At this receiver side, the refection factor is one. After two propagation delay periods, the signal appears back at the microcontroller interface. When the signal appears at the microcontroller, its magnitude is equal to 3.2 V. After three propagation delay periods, a 0.9 V signal appears at the ADC interface. Figure 5 illustrates the signal's reflection and ringing at the microcontroller driver and ADC receiver.
Figure 5: A timing diagram of the signal's theoretical reflections
and the actual ringing at the ADC receiver and microcontroller driver.
(Click on image to enlarge)
(Part 2 of this article will look at using terminations to tame reflections; you can read it by clicking here.)
(A special "thank you" goes to Tom Hendrick at Texas Instruments for his guidance and contribution in defining this topic and setting up our test.)
Reference:
1. "High Speed Digital Design: A Handbook of Black Magic," Howard Johnson, Prentice Hall, 1993
2. "Managing Signal Quality," Mentor Graphics/Xilinx, 2005 www.xilinx.com/publications/xcellonline/xcell_53/xc_pdf/xc_mentor53.pdf
About the Authors
John Zhonghua Wu is a senior application engineer at Texas Instruments. He holds a Bachelor of Engineering degree in Electronic Engineering from University of Dalian, P.R. China, and a Master of Science degree in Electronic Engineering from the Chinese Academy of Sciences.
Bonnie Baker is a senior application engineer at Texas Instruments. She holds a Masters of Engineering degree in Electrical Engineering from the University of Arizona, and is the author of many articles and columns.
