(Editor's note: Although Planet Analog usually does not cover internal IC-design issues, this article discusses an innovative, multiple-voltage level-shifter topology which demonstrates the dependence of digital circuits on analog fundamentals such as rise/fall times, capacitance, and current/voltage sourcing/sinking.)
VLSI technology is enabling the realization of complex System on Chip (SoC) designs where different parts of a system, such as analog and digital circuits, as well as passive components, are integrated onto a single chip. In such SoCs, different parts of the chip run at different voltages to achieve optimum speed/power ratios, and it is very common to have two or more voltage domains in a single chip. For communication among the different parts of a chip having different supply voltages, level shifters are required to convert the logic signal from one voltage level to the other voltage level. Level shifters are also required at the pad-ring and chip-core interface, where low-voltage logic signals from chip core are shifted to the higher voltage levels at which the pad ring is operating.
Figures 1a and 1b show the interface between two modules operating at 3.3 V and 5.0 V respectively.
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Figures 1a and 1b: Interface of two different modules using level shifters
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Figure 2 shows the schematic of commonly used level shifters for interfacing the modules operating at different voltages. Such a level shifter requires two voltage supplies: the input-logic signal-voltage supply (VDDL) and output-logic signal-voltage supply (VDDH).
Figure 2: Schematic of a conventional level shifter
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Also, in a multi-chip system where different chips operate at different voltage supplies, the level shifter enables communication between different modules by shifting the lower logic voltage to a higher logic voltage. A typical example of such a system could be a mobile phone platform which generally has four main modules: RF chip, baseband processor, power management chip (PMC), and power amplifier (PA). Each of these four modules operates at a different power-supply supply, yet they need to communicate with each other.
Figure 3 shows an example of a multi-voltage system where four modules, operating at different supply voltages, are interacting with each other using the conventional level shifter shown in Figure 2. As mentioned earlier, both VDDL and VDDH are required with conventional level shifters. Any module which needs shifting of a lower supply signal to a higher supply signal, will require all the lower supply voltages as well.
Figure 3: Interfacing of four different modules using conventional level shifters
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For example, a module operating at 3.3 V communicating with the other three modules of 1.2 V, 1.8 V and 2.5 V will require all three supplies. It is obvious from the example shown in Figure 3 that the pin count of the system is increased significantly if the conventional level shifter is used.
Similarly in a multi-voltage SoC, there may be thousands of signals requiring level shifters for transferring the signals between modules. This leads to huge congestion in the supply-line routings. In both cases (SoC or multi-chip system), the situation becomes worse as the number of supplies increases, which ends up adding further complexity and cost to the overall system.
Using open-drain signaling for level shifting
In order to remove the lower power supply (VDDL) from the level shifter, open-drain signaling is often used to communicate between two chips or modules operating at different power supplies. As shown in Figure 4, open-drain signaling doesn't require a pull-up (PMOS) transistor, and hence the drain of the NMOS transistor is left floating or open.
Figure 4: Open-drain signaling for interfacing two modules
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This drain is connected at the higher power supply through a pull-up resistor located either on-board or on-chip. The logic signal coming from the module operating at VDDL is shifted to VDDH without requiring VDDL in the higher supply module. Though this technique gets rid of VDDL from the level shifter, due to the presence of the pull-up resistor, it suffers from static power consumption during logic 0 at OUTL.
A higher value pull-up resistor can be used to cut down the static power but then a higher RC-time constant will limit the speed of operation (Figure 5). Thus, open drain has a tradeoff between power and speed. The open-drain signaling might not be feasible in today's chip interfaces where a bus is required to run at a few hundred MHz with low static-power consumption. Due to these issues, there is a need for a single supply level shifter that can run at the required speed without any static power consumption.
Figure 5: Effect of RC-time constant on speed
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Single-supply level shifter
Figure 6 shows an example of the multi-voltage system of Figure 3, in which modules working at different supplies are interacting with each other using the single-supply level shifter. The single-supply level shifter allows communication between modules without adding an extra supply pin.
Figure 6: Interfacing of four different modules using single-supply level shifter
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Similarly, in an SoC, routing congestion is reduced, resulting in less complexity and reduced chip area. The single-supply level shifter, when used in I/Os, makes the interfacing of signals compatible to other I/O interfaces and can simultaneously handle various signal levels without requiring any extra supply pins.
The single-supply level shifter (References 1 and 2) is shown in Figure 7. The main idea of this design is to recover the lower supply level from the input logic signal itself then used in the circuit. When the input signal is at logic high, i.e. VDDL (which is assumed to be a lower supply level), MN2 turns ON and pulls node OUTB to VSS.
Figure 7: The single-supply level shifter
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This turns ON MP1, which pulls the output node OUT to VDDH (which is assumed to be a higher supply level). With OUTB at VSS, MN1 will be OFF and MP3 will be ON, which charges node VC to the input signal voltage VDDL. VDDH being higher than VDDL, MN3 will remain OFF. Thus, with IN at VDDL, OUT will be at VDDH.
In the second case, when IN is at logic low (VSS), initially VC will remain at VDDL, turning ON MN3. MP3 is kept weak as compared to MN3 to prevent the node VC from getting discharged before node OUT is discharged. On the other hand, MP3 should also be strong enough to charge node VC at supply level of IN (VDDL) within ON period of the input signal. Hence, the size of both MN3 and MP3 depends upon the frequency of operation and should be chosen properly during design.
As node OUT starts discharging towards VSS through MN3, MP2 starts charging node OUTB towards VDDH. As node OUTB charges, MN1 turns ON and starts discharging node OUT towards VSS. Thus, with IN at logic low, OUT will also be at logic low.
In both cases, the current flows only during the transitions and not in steady state. The use of MOSCAP MPC is a holding capacitor that serves two purposes. It helps prevent the discharge of node VC through MP3 and also acts as a startup when the circuit is powered up. When VDDH is ramping up and IN is at logic low, there is a possibility that node OUT may start following VDDH as node VC is floating, thus generating a wrong output logic. Due to MPC, VC follows VDDH and turns ON MN3 to provide a discharge path for OUT making sure that it is pulled down to logic low.
The value of capacitance MPC should be such that MP3 should be able to charge node VC within the ON period of the input signal IN, and then hold it. At lower frequency, the input signal may remain in low state for a long time, which might discharge node VC completely through MP3 leakage path. In this case MN3 will completely turn OFF disconnecting OUT from IN.
The state of OUT does not change as it gets latched with the help of MP1, MP2, MN1 and OUT remain at logic low. The body of PMOS transistor MP3 is connected to VDDH in case of power sequencing and is defined in such a way that VDDH ramps up before the input signal supply (VDDL). Otherwise, the body of MP3 should be connected to VC in order to prevent any leakage through body diode when input is at logic high while VDDH has not ramped up fully.
The simulation results of the single-supply level shifter are shown in Figure 8. The circuit was simulated at three different input logic levels, 1.2 V, 1.8 V and 2.5 V, with VDDH = 3.3 V. The profile of VC can be observed, which is charged to VDDL at the rising edge and held at slightly lower level after the input settles. The holding capacitor (MPC) value in this case was set to 100 fF.
Figure 8: Simulation results of single-supply level shifter
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References
1. US Patent 7,009,424: Single Supply Level Shifter
2. Khan Q. A., Wadhwa S. K., Misri K, "A Single Supply Level Shifter for Multi-Voltage Systems," 19th International Conference on VLSI Design, Jan. 2006, India.
About the authors
Qadeer Khan is a graduate student at School of EECS, Oregon State University, working towards his master's degree with specialization in Analog and Mixed Signal IC design. He received a Bachelor's Degree in Electronics and Comm. Engineering from Jamia Millia Islamia University, New Delhi in 1999. From 1999 to 2005 he worked with Freescale Semiconductor, India as a Lead Engineer where he was involved in designing of mixed-signal circuits for baseband and network processors, and full-chip integrated solutions for high-voltage motor drives. From 2006 to 2007, he worked for Siways Microelectronics, India where he worked on full-chip, high-voltage, switching-power converters. He has published papers in various IEEE conferences and holds eight US patents.
Sanjay Wadhwa is working as a design manager in Freescale Semiconductor, Noida, India. He graduated in Electronics and Communication Engineering from National Institute of Technology, Kurukshetra, India. He is working in the field of analog and mixed-signal designs, mainly clock-generation circuits. He has published 10 papers in various VLSI conferences and holds six US patents.
Kulbhushan Misri works as a Distinguished Member of the technical staff at Freescale Semiconductor based in Noida, India. He is a graduate of the Regional Engg College, Srinagar. His field of interest is analog mixed-signal design with a focus on low-power and high-speed circuits. He has eight patents along with many publications.
