Adaptive computing machine (ACM) technology represents a new trend toward eliminating the design barriers for cellular phones by turbocharging functional performance and extending battery life. ACM hands the designer a virtual carte blanche for incorporating any and all features and functions into a handset. Unlike a conventional ASIC-based design, ACM gives the designer a great deal of latitude because it permits the designer to download new "hardware" constantly onto an adaptive silicon chip and, on-the-fly, run virtually any algorithm required at any given moment on its own customized hardware.

ACM technology extends conventional DSP functionality by adding a greater degree of freedom to cellular phone designs that have, to date, only been attempted by changing software. Adapting the ACM chip architecture as necessary brings many new system features within the reach of a single ACM-based platform.

For instance, within a handset, the hardware could adapt to be a handwriting or voice recognition system, or it could do on-the-fly cryptography. The system engineer can also design in highly improved voice quality. Because of its adaptability, ACM technology can give the cell phone user the ability to make or receive calls anywhere in the world. CD-quality music via the Internet can also be received via an ACM-based handset, or virtually any type of information or entertainment can similarly be downloaded.

Performing those and other functions at hardware speeds can benefit users while greatly reducing power consumption within battery-driven products. The on-the-fly adaptability also provides multimode handset operation that is impervious to constantly changing standards or newly improved software for such functions as vocoders.

In particular, ACM technology significantly reduces power consumption and is especially valuable to CDMA handset designs using the Qualcomm code-excited linear predictive coding (QCELP) speech compression algorithm. The QCELP vocoder is among the more challenging aspects of newer-generation handset designs.

Vocoders are a class of speech-coding systems that perform several key operations. They analyze the voice signal at the transmitter, transmit parameters derived from the analysis, and then synthesize the voice at the receiver using those parameters. All vocoder systems try to model the speech-generation process as a dynamic system and then try to quantify certain physical constraints of the system. Those physical constraints are used to provide a parsimonious description of the speech signal.

The most popular among the vocoding systems is the linear predictive coder (LPC), and the most advanced version is code-excited LPC. In this method, the coder and decoder have a predetermined codebook of stochastic (zero-mean white Gaussian) excitation signals. For each speech signal, the transmitter searches through its codebook of stochastic signals for the one that provides the best perceptual match to the sound when used as an excitation to the LPC filter.

The index of the codebook where the best match is found is then transmitted. The receiver uses the index to pick the correct excitation signal for its synthesizer filter. Code-excited LPC (CELP) coders are extremely complex and can require more than 500 million multiply and add operations per second. They can provide high quality even when the excitation is coded at only 0.25 bit per sample, and they can achieve transmission bit rates as low as 4.8 kbits/s.

In a procedure for selecting the optimum excitation signal, an example is the coding of a short, 5-ms block of speech signal. At a sampling frequency of 8 kHz, each block consists of 40 speech samples. A bit rate of one-quarter bit per sample corresponds to 10 bits per block. Therefore, there are 1,024 possible sequences of length 40 for each block.

Each member of the codebook provides 40 samples of the excitation signal with a scaling factor that is changed every 5-ms block. The scaled samples are passed sequentially through two recursive filters, which introduce voice periodicity and adjust the spectral envelope. The regenerated speech samples at the output of the second filter are compared with samples of the original speech signal to form a difference signal. The difference signal represents the objective error in the regenerated speech signal. This is further processed through a linear filter, which amplifies the perceptually more important frequencies and attenuates the perceptually less important frequencies.

Qualcomm's 13-kbits/s QCELP is a vector quantizer-based speech codec. It is also a multirate speech codec. That means that as it analyzes the digitized speech, it determines the best compression ratio to be used for the segment of speech. The analyzer breaks up the speech segments into 20-ms segments or 160-sample segments at an 8-kHz sampling rate.

The analyzer's purpose is to compute the smallest data rate that keeps the synthesized quality high while using the minimum number of bits to represent the speech. For example, a full frame rate with 256 bits in the frame produces an instantaneous data rate of 13.3 kbits/s. The rate determination algorithm computes a frame rate for each frame.

There is another algorithm, commonly refered to as the rate reduction algorithm, that can be used to change the rate that is chosen to a lower average rate. Essentially, this algorithm is used when the basestation decides that some of the channel bandwidth needs to be used for other data-related functions or that the channel is impaired and cannot sustain the normal full-rate data rate. Computations for the rate determination and reduction algorithms demand the accuracy of 32-bit arithmetic to pass the minimum requirements. Thus, single-cycle 32-bit multipliers, dividers and 70-bit accumulators are required for processing this section of the code.

A QCELP engineering analysis was used to compare power consumption among DSP-only, DSP and ASIC, and DSP and ACM-based QCELP vocoder system designs. Eight inner code loops or algorithms consume most of the power in the QCELP algorithm. Those are code book search, pitch search, line spectral pairs (LSP) computation, recursive convolution and four different filters.

The entire QCELP algorithm running on a typical DSP-only core consumes about 84 milliwatts of power. Based on a 0.25-micron CMOS system-on-chip, the embedded DSP and memories use about 4 square millimeters of silicon area.

Power balance

Moving the eight most power-consuming QCELP algorithms to ASIC cores, on the other hand, consumes only 19 mW (3 mW for the ASIC cores, 16 mW for the DSP), but takes 23 mm2 of silicon. Here, the ASIC cores run the eight inner code loops while the DSP core runs the remaining QCELP code. The ASIC solution's silicon area is considerably larger than the DSP version's, but at a major power savings. However, the ASIC approach for cellular phone design is becoming impractical due to ever changing algorithms and standards, and the demand for more functionality.

When the designer augments DSP functionality with an ACM, the QCELP power consumption can be significantly pared down while adding only a minimal 5 mm2 ACM chip. In this example, the same eight most power-consuming QCELP algorithm routines are taken away from the DSP operations (same algorithms as the DSP and ASIC solution) and ported into the less power-hungry ACM engine, which also consumes only 3 mW. By doing so, the designer transfers 68 mW of power out of the DSP operation, which earlier consumed 84 mW. Thus, the DSP/ACM-based QCELP vocoder design consumes 19 mW.

The software-programmable ACM device exhibits the power characteristics of an ASIC, yet is comparable in size to the DSP.