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16bit data converters follow integration trend

A new class of standard product data converters based on the continuous-time sigma-delta (CTSD) architecture was unveiled by Analog Devices (ADI) at Electronica today.

Billed as the industry's lowest noise, wide bandwidth CTSD analog-to-digital converters (ADCs), the 16bit AD9261 and dual channel 16bit AD9262 are the first of a family of CTSD ADCs and marked a first for another reason that ADI's Bill Schofield explained. Referring to the CTSD architecture, he said: “This technology been used many times before ” it is the technology of choice in mobile handsets, but it is most usually found as an integrated solution. This is the first time we have taken an integrated solution and made it a standard product.” This being the case, designers should expect significant system simplification from this, as well as performance gains and cost saving compared to a discrete solution.

According to Nitin Sharma, product marketing manager for ADIs high speed converters, the AD9262 achieves the lowest noise performance for a 16bit ADC at 86-dB dynamic range for an input signal bandwidth of up to 10MHz ” the range at which target applications such as wireless infrastructure, medical imaging and industrial instrumentation typically operate. Another aspect of the ADC's performance is its power efficiency. According to Sharma, compared to a state of the art pipeline coverter at a similar performance level and bandwidth, the A/D core within the AD9262 is two to three times more power efficient.

Analog Devices considers that in terms of performance, this data converter family sits somewhere in the middle between a SAR architecture (high resolution, low noise, limited bandwidth, low power) and a pipeline converter architecture (high sample speed so they can digitise wideband signals, but the trade-off is noise performance and power). SAR ADCs are usually used for industrial controls and data acquisition systems where precision and low-noise are key. Pipeline ADCs are typically used for wireless infrastructure, video processing and other applications where performance requirements dictate wide bandwidth.

Aside from the performance metrics, the CTSD ADCs are in Schofield's words 'not just a new component, but a new way of thinking about a system'. From an integration point of view, among the CTSD architecture's benefits are an integrated loop filter; built-in low pass filtering, meaning that antialiasing filters aren't required; and no need for a driver amplifier or any variable gain in front of the A/D for many applications.
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In addition to the AD9261 and AD9262, there's a 640MS/s modulator core and PLL clock multiplier – the AD9267 – that gives designers the flexibility to offload signal processing functions to an FPGA or other processor. The AD926x CTSD ADC family is sampling now and will be available in volume production in April 2009.

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