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3 Circuit Protection Innovations Designed to Protect Wearable Technologies

Today’s wearables demand lower capacitance, lower clamping voltage, and a smaller form factor.

You may have been told not to wear your heart on your sleeve. But now there’s technology that allows you to monitor your heart from your sleeve.

We’re talking about wearable electronics or wearable computing — the hottest consumer electronics sector on the market. Wearable gadgets are interactive devices that often track or monitor information about the wearer. Popular wearables include smart glasses, ring/finger-worn scanners, footwear, wristwear (e.g., electronic watches and wristbands), neckwear, headbands, and the upcoming “smart textiles.”

While it might seem like something out of a science fiction novel, wearables like smart glasses and fitness wristbands are quickly becoming part of our everyday life. According to marketsandmarkets.com, the wearable technology market will be worth $8.36 billion by 2018. That article notes that wristwear accounted for the largest share of market revenues in 2012, with total revenues of the most established wearable electronics exceeding $850 million.

Wearable technology presents an interesting challenge to circuit designers. Why? Think about how these devices are designed to get up close and personal with the consumer. Because they are meant to be worn next to the skin, there’s a significant risk of exposure to user-generated static electricity. Unfortunately, a simple human touch can generate a transient electrostatic discharge (ESD). Without proper protection, any of the sensor circuits, battery-charging interfaces, buttons, or data I/Os could provide a path for ESD to enter the wearable device and cause irreparable damage.

Fortunately, such companies as Littelfuse Inc. are continually investing in the development of new processes that enhance their semiconductor-based ESD protection components. Wearable device manufacturers benefit from an expert supply of circuit protection technologies because they help improve the safety and reliability of their products.

Consider some recent component innovations that can benefit the wearable technology market:

  • Lower capacitance to avoid interfering with high-speed data transfer. ESD protection devices must offer circuit protection without interfering with the daily functionality of the circuit being protected. For example, on an RF interface (e.g., Bluetooth or ZigBee) or a wired port like USB 2.0, the ESD protector must not cause distortion or loss of strength of the data signals. To provide signal integrity, the capacitance of the ESD protector must be minimized without compromising protection levels. Littelfuse’s SP3022 Series TVS Diode features a capacitance value of 0.35 pF to ensure that it will remain “invisible” to high-speed signals.
  • Lower clamping voltage to protect even the most sensitive circuits. If an ESD event occurs, the primary job of the ESD protector is to divert and dissipate as much of the ESD transient as possible. This characteristic is improved by reducing the on-state resistance or the dynamic resistance. By decreasing the dynamic resistance, the ESD protector carries significantly more of the surge current than the circuit being protected. By doing this, it reduces the electrical stress on the integrated circuit and ensures its survival. For example, Littelfuse’s SP3014 Series TVS Diode Array has a dynamic resistance value of less than 0.1Ω to provide best-in-class performance.
  • Smaller form factors to fit the limited board space available in the wearable devices. No matter how well a protection device performs, it’s not very useful if it can’t fit into the application it’s meant to protect. As wearable devices get thinner and smaller, the circuit boards will have minimal space available to accommodate ESD protection solutions. Discrete diodes are the best solution to this potential design challenge because they give design engineers exceptional board layout flexibility. The SP1020 (30 pF) and SP1021 (6 pF) Series Diodes from Littelfuse are contained within the 01005 package outline to minimize the amount of space they occupy. In addition, the SP1012 Series (Figure 1) packs five bi-directional channels of protection in a space-saving 0.94 x 0.61 mm package outline for applications that demand reduced part counts and smaller protection device footprints.
Figure 1

SP1012 Series five-channel bidirectional TVS diode arrays offer robust protection against destructive electrostatic discharges.

SP1012 Series five-channel bidirectional TVS diode arrays offer robust protection against destructive electrostatic discharges.

It’s clear that wearable technology is here to stay. Wearable devices will continue to challenge the designers who have to make sure that they function as expected, regardless of the user’s activity level or how often they are subjected to ESD transients. Manufacturers of ESD protection devices will continue developing protection technologies that do not interfere with the wearable device’s core functionality — helping wearable device manufacturers deliver reliability and value to the consumer.

76 comments on “3 Circuit Protection Innovations Designed to Protect Wearable Technologies

  1. amrutah
    July 27, 2014

    “Lower capacitance to avoid interfering…”

    @James:  Thanks for the post and for letting us know about the challenges in wearable tech.

        For the IC we design, we do have ESD for all the pins.  These ESD devices are large compared to the area of the devices that it is intended to protect.  Large surge currents calls for more larger devices, which means more reverse biased diodes, more capacitance.  What is the benchmark when we say High/Low capacitance is needed?

  2. amrutah
    July 27, 2014

    “Discrete diodes are the best solution to this potential design challenge …”

    @James: This is interesting.  If I am not wrong, the idea you are proposing here is to have the discrete TVS diodes on each of the pins of the IC?  But it will call for more of board area and also the list of BOM will increase.  Is there something that I am missing?

  3. amrutah
    July 27, 2014

    James:  Most of the ESD protection schemes on chip use the series current limiting resistors for ESD (which may effect the actual signal).  And more the resistor (with the spec boundaries of the signal), the better it is.

    When you say the “characteristic is improved by reducing the on-state resistance or the dynamic resistance…” , you are referring to resistance offered by the Discrete TVS diodes solution?

  4. amrutah
    July 27, 2014

    @James: What are the levels of HBM or CDM tolerance levels of these TVS diodes?

    How do we say what is the best suited HBM for the wearable tech?

  5. Netcrawl
    July 27, 2014

    @Amrutah, circuit protection designed can be very effective and can do a very great job in protecting your devicec but only if you do some design and planning upfront, we need to realize that there is no 100% protection here, if we design to protect against particular event it's always possible that something more severe or devastating could happen. We need to know the hazards we intend to protect against.  

  6. goafrit2
    July 27, 2014

    I think a better design paradigm for wearables will be asynchronous strategy which automatically eliminates all these parasitic issues associated with capacitance.

  7. Netcrawl
    July 27, 2014

    @amrutah to protect wearables against hazards such as ESD, we need to choose circuit protection design that offers low capacitance, low capacitance could help preserve signal integrity and at the same time provide protection from electrostatic discharge.

    For overvoltage conditions or incurrent supply voltages, a zener diode and polymeric could be a great solution.

  8. geek
    July 28, 2014

    “to protect wearables against hazards such as ESD, we need to choose circuit protection design that offers low capacitance, low capacitance could help preserve signal integrity and at the same time provide protection from electrostatic discharge.”

    @Netcrawl: Doesn't the low capacitance affect performance in any way? From what I know, capacitance is linked directly with battery storage. So in any way, will the storage capacity or the rate of charge will be affected by it which may eventually affect performance?

  9. geek
    July 28, 2014

    @amrutah: It may be a very naive question here, but if you're suggesting large devices, that does that not affect their perfomance in terms of being wearable and being able to integrate with the environment? The whole idea of wearable devices is to have smaller devices that can fit well into the user's environment without being an obstruction.

  10. jim_colby
    July 28, 2014

    Historically, your comments are correct.  In the past, in order to get good ESD performance (low clamping voltage), we typically have needed large diode structures.  However, wafer fab processes and back end assembly capabilities have been improving over the recent years, and it is now possible to have very good and robust ESD protection in small form factors.  For example, our upcoming general purpose 01005 diode will be able to withstand 30kV contact discharge (IEC 61000-4-2) and have a dynamic resistance value of less than 1 ohm.

  11. jim_colby
    July 28, 2014

    Similar to the question on the size of ESD protection devices, advancements have been made with respect to capacitance and ESD performance.  By this, I mean that there is no longer a trade off between these two characteristics.  New wafer fab processes have been developed, for example, that allow us to create a protection device with 0.5pF of capacitance, and yet, still have less than 1 ohm of dynamic resistance.  So, we don't store any charge, or affect high-speed signal integrity, and have a good, low-clamping device.

  12. jim_colby
    July 28, 2014

    With respect to Polymeric devices and zener diodes as alternatives to the Semiconductor solutions described in this blog you are correct – to a point.  It is important to recognize that these three solutions have very different characteristics; among them is dynamic resistance.  For chipsets with robust on-chip protection (per Human Body Model), then Polymers and Zeners are sufficient to protect them.  However, newer ICs made on very dense topologies (45nm, 22nm, etc.) are very sensitive to ESD pulses (or any EOS for that matter), and typically require the lower dynamic resistance associated with Semiconductor ESD devices.  In summary, the solution needs to match the needs of the IC that is being protected.

  13. jim_colby
    July 28, 2014

    The key here is to recognize that Human Body Model is a designation for the ESD robustness of the ICs that run the application (processor, memory, ASIC, etc.).  It is not a designation for the board-level ESD protection.  These devices are typcally characterized to the IEC 61000-4-2.  Even though this is a system-level specification, it allows us to determine whether the ESD device will survive the system-level transient, and ideally, also protect the system.  So, board-level ESD devices will not have HBM, MM, nor CDM values, as they are not considered to be ICs.  You can determine their robustness by getting the IEC 61000-4-2 rating (8kV contact, etc.) and you can determine how well they protect by getting the dynamic resistance value (1 ohm, 0.5 ohm, etc.).  For Wearable Technology, we'll want a high IEC rating, and low dynamic resistance.

  14. jim_colby
    July 28, 2014

    You are exactly right.  Designers should consider their ESD protection early in the design cycle so they can choose the right protection device, but also, they can choose the optimal layout and location before their options get taken away by other components (common mode chokes, passives, transformers, etc.).  The ideal location for the ESD Diodes is right behind the connector (where ESD enters the application) and right next to the signal line that is being protected.  A long stub trace will add inductance which can cause inductive overshoot during an ESD event (and lead to damage of the IC).

  15. jim_colby
    July 28, 2014

    That is correct.  Our dynamic resistance specification is a measure of how much the ESD Diode has when it is turned on.  Ideally, this would be zero to shunt all of the transient current to ground.  But, this is not possible.  So, we do the best we can to design parts with low dynamic resistance.  This will ensure that as much of the ESD transient as possible is steered to ground and away from the protected IC.

  16. jim_colby
    July 28, 2014

    We won't typically need board-level ESD Diodes at each of the IC's pins.  Rather, we're going to want to determine which of those pins has exposure to the outside of the application.  Typical circuits include audio, button/switch control, USB and other data buses.  You are right that adding these discrete devices will take up board space, so we are concentrating efforts on reducing their size – we're down to 0201 and 01005 outlines now.  If appropriate, there are also some very space efficient multi-channel arrays available.

  17. samicksha
    July 29, 2014

    Thank You Jim for all the good comments here, i guess one of the point here is that next generations of portable devices are very sensitive to damage from ESD voltage as new coming IC employ lower working voltages like we have in smartphones.

  18. jim_colby
    July 29, 2014

    You are exactly right.  ESD Diode manufacturers will continue to work on developing lower-clamping products, and will need to work with board-level Designers to ensure that good circuit layout practices are followed; in order to ensure the ultimate reliability of the application.

  19. vasanjk
    July 30, 2014

    Jim,

    Your post is very relevant as on date as wearables are emerging and rapidly evolving.

    It is important to implement circuit protection early on, may be, from day one of schematic design. It pays to leave couple of 0805 or 0603 package footprints at strategic places in the design.

  20. jim_colby
    July 30, 2014

    You make a very good point.  If there is not enough time to do a complete ESD protection analysis at the early stages of the board layout, it should be possible to at least put sockets at each I/O or location where ESD will be expected to get into the application.  I would say that we may want to consider 0402 or even 0201 as the available board space will be very limited.  These footprints are very common today, and parts can be readily sourced from a number of suppliers (including general purpose as well as low capacitance diodes).

  21. amrutah
    July 30, 2014

     “high IEC rating, and low dynamic resistance”

    @jim_colby:  As you pointed out, I was thinking about the IC level ESD protection and devices.  Now I understand, Thanks for the information. 

  22. amrutah
    July 30, 2014

    @tzubair: I was largely considering the ESD protection internal to IC and not at the board level.  Another important thing when I mentioned the ESD devices to be “large”, it was in relation to the devices it is intended to protect.  something like protecting a device 500nm long with a 100um wide transistor, which adds a lot of capacitance to the node.

  23. vasanjk
    July 30, 2014

    Jim

    In order to facilitate EMI , ESD protection even at a later stage in the design process, ferrite beads, decoupling caps and ESD , TVS devices can be incorporated and left there in the PCB. In case of the beads one could use a 0 ohm resistor, if ferrite bead function is not necessary.

  24. jim_colby
    July 31, 2014

    These are all good points.  Like other engineeing problems, there will be multiple solutions available for ESD.  It will be important however, to determine which is best based on circuit considerations, cost, board implementation, etc.  For example, a ferrite bead can be an effective ESD remedy, but it must be remembered that it is not appropriate for high-speed circuits like USB 2.0, USB 3.0, HDMI, etc.  In these cases, the inductance that will remediate the ESD pulse, will also cause signal integrity issues.  For this problem, it is typically better to use a low capacitance (< < 1pF) in parallel to shunt the ESD transient away from the IC.  The low capacitance will not interfere with the data transfer, and the clamping action of the ESD Diode will protect the IC.

  25. chirshadblog
    July 31, 2014

    @Jim: There are solutions written down on many forums but how many have been tested is the question 

  26. chirshadblog
    July 31, 2014

    @vasanjk: Have you tried this mate ? I think I tried exactly the same but didn't work as expected. 

  27. vasanjk
    July 31, 2014

    chirshad

     

    These are proven techniques helping products pass various quality certifications. They are essential ingredients of any successful design.

    Believe me, products work in rigorous environments without any problems because of such,implementations.

  28. chirshadblog
    July 31, 2014

    @Jim: Yes a good background research job has been done initially and because of that things are easy now

  29. vasanjk
    July 31, 2014

    I have used all these and other techniques to get a medical device pass EMI/EMC certification in straight two weeks. Littlefuse and Wurth have products that help us to get through such stringent standards.

     

     

  30. SunitaT
    July 31, 2014

    According to marketsandmarkets.com, the wearable technology market will be worth $8.36 billion by 2018.

    @James, thanks for the post. I am sure these numbers will encourage many other palyers to jump into wearable technology market and thus it will help create new innovative products.

  31. chirshadblog
    July 31, 2014

    @amrulah: Thank you for sharing it mate. Was really helpful 

  32. SunitaT
    July 31, 2014

    However, wafer fab processes and back end assembly capabilities have been improving over the recent years, and it is now possible to have very good and robust ESD protection in small form factors.

    @jim_cobly, thanks for this update. I wasn't aware of the latest trends in ESD protection. I am curious to know typically how much of area shrinkage we can get with the latest technology in ESD.

  33. SunitaT
    July 31, 2014

    I think a better design paradigm for wearables will be asynchronous strategy which automatically eliminates all these parasitic issues associated with capacitance.

    @goafrit2, I am curious to know what is meant by asyncronous strategy and how it will help us automatically elimiates parastic issues because parastitic effect will be present in both synchornous and asynchronous systems. 

  34. samicksha
    July 31, 2014

    If we talk about cost TVSs are low in cost and can be placed close to the system's I/O connectors.

  35. samicksha
    July 31, 2014

    @vasanjk: How do you suggest to decide whether to for unidirectional or bidirectional TVSs.

  36. SunitaT
    July 31, 2014

     The whole idea of wearable devices is to have smaller devices that can fit well into the user's environment without being an obstruction.

    @tzubair, true. But what amrutah was trying to tell was that to tackle large surge currents we need bigger devices which increases the device size. But looks like with new technology we can have smaller ESD devices which can protect large surge currents.

  37. SunitaT
    July 31, 2014

    How do you suggest to decide whether to for unidirectional or bidirectional TVSs.

    @sammicksha, usually unidirectional TVS will be used for dc supplies and bidirectiional is used in ac lines generally but you can generally always use bidirectional in both cases.

  38. vasanjk
    July 31, 2014

    Samicksha

     

    Good question. I may not be an expert in this field. Jim would be able to throw some light on this.

     

    Sunitah's comments are true but ESD noise could have different forms and the right choice depends on the noise signal in question.

  39. geek
    July 31, 2014

    “it was in relation to the devices it is intended to protect.  something like protecting a device 500nm long with a 100um wide transistor, which adds a lot of capacitance to the node.”

    @amrutah: Thanks for the clarification. I thought you were referring to the size of the overall circuit in this case. In relation to the size of devices, it shouldn't really matter much.

  40. geek
    July 31, 2014

    “However, wafer fab processes and back end assembly capabilities have been improving over the recent years, and it is now possible to have very good and robust ESD protection in small form factors”

    @jim: Does the small form factor has any downside to it? Is there a compromise required in terms of the performance to accomodate the small form factor?

  41. Sachin
    July 31, 2014

    Does the small form factor has any downside to it? Is there a compromise required in terms of the performance to accomodate the small form factor?

    @tzubair, I dont think there is any downside to it. I think because of new inventions in manufacturing  methodologies we are able to reduce that form factors which is always a welcome move. I think as we shrink the transistor sizes we might be able to get better form factor in future.

  42. jim_colby
    August 1, 2014

    I would just expand on this with a couple quick additions.  Unidirectional diodes are typcially used for DC circuits (including pushbuttons, switches, etc.) as well as digital circuits where there is no negative voltage as part of the signal (USB, HDMI, etc.).  Bidirectional diodes are used in AC circuits which includes any signal with a negative component greater than -0.7V, including audio, analog video, legacy data (CAN, RS-485, etc.) and a number of RF interfaces (cellular, Bluetooth, NFC, etc.).

  43. jim_colby
    August 1, 2014

    @chirshadblog:  The complete ESD design requires not only the correct suppression device, but good board layout as well.  As mentioned elsehwere in these notes, the ESD suppressor should be located as close to the connector (ESD entry point) as possible.  Also, if there is a stub trace from the protected line to the suppressor, it should be as short as possible.  This will help to minimize inductive overshoot, which adds to the voltage (stress) that the IC can experiece.  Please feel free to contact me directly for more information.  My e-mail address can be found in my Bio.

  44. goafrit2
    August 3, 2014

    These ESD devices are large compared to the area of the devices that it is intended to protect.  Large surge currents calls for more larger devices, which means more reverse biased diodes, more capacitance. 

    That could be challenging for the consumer industry where you need to get more from a wafer lot.

  45. goafrit2
    August 3, 2014

    >>  If I am not wrong, the idea you are proposing here is to have the discrete TVS diodes on each of the pins of the IC?  But it will call for more of board area and also the list of BOM will increase.  Is there something that I am missing?

    Besides the cost model of using a discrete component, it increases testing and production. One has to look at the cost-to-benefit analyses and the overall effectiveness level of the components to see they matter. If you are using the product in a toy, that may not be important. As critical systems, that is huge.

  46. goafrit2
    August 3, 2014

    And more the resistor (with the spec boundaries of the signal), the better it is

    We need to remember dynamic power consumption. It may not be always that the more the resistor, the better. One must examine the system application and the cost element to see if that makes sense.

  47. goafrit2
    August 3, 2014

    For overvoltage conditions or incurrent supply voltages, a zener diode and polymeric could be a great solution.

    That will mean we will need to have discrete components owing to the challenges of making any of these systems in the integrated ways.

  48. goafrit2
    August 3, 2014

    >> The whole idea of wearable devices is to have smaller devices that can fit well into the user's environment without being an obstruction.

    That is the premise upon which wearables are designed. One must design and develop these systems under tight cost-budget and tight-real estate. If there is liberty on cost, size and power-expense, then we are not talking about wearables.

  49. goafrit2
    August 3, 2014

    >> According to marketsandmarkets.com, the wearable technology market will be worth $8.36 billion by 2018. 

    I think this number is very small. Apple by 2018 is expected to make $5B in this sector. IHS thinks this will be a $12b business in 2017.

  50. goafrit2
    August 3, 2014

    >> I am curious to know what is meant by asyncronous strategy and how it will help us automatically elimiates parastic issues because parastitic effect will be present in both synchornous and asynchronous systems. 

    Asynchronous does not use clock and is based on event-driven paradigm. That means there is no element of time and that will mean you do not have to deal with delays and parasitics. Under asynchronous design, there is no issue of delay and parasitics.

  51. goafrit2
    August 3, 2014

    >> I dont think there is any downside to it.

    There is actually. As you reduce form factor which means smaller transistors you are going to deal with parasitics and static power dissipation. As devices go lower, many issues come up. The balance comes down to cost and performance. There are benefits for being small. Yet, there is cost to be paid.

  52. amrutah
    August 3, 2014

    @jim_colby: I agree that we are trying to get the form-factor of the TVS diodes small, but I see that the routing might be a limitating factor.

      If we are to protect the pins, then we have to place the diode and also route a wide ground plane for the current return path.  Can the ground routing be a limiting factor?

  53. amrutah
    August 3, 2014

    @goafrit2:  I have designed applications, where a comparator is used for monitoring some external parameter.  The on-chip size of the comparator+reference is 40umx60um whereas the input and the output ESDs' take up 120umx80um.

      I agree, the area is sensitive but can't ignore the ESD.

      

  54. jim_colby
    August 4, 2014

    We are not dealing with a large amount of current for a long duration.  Rather, we need to move the ESD charge from the protected circuit to the ESD reference, in a very short amount of time (<200ns).  So, the width of the trace to gound is not the overriding factor.  Instead, it is the length of the trace.  This should be kept as short as possible to limit parasitic inductance.  So, we're more concerned with inductance rather than DC resistance of the ground trace.

  55. etnapowers
    August 4, 2014

    That's true , it is one of the most common facts in electronics: the advantages of reducing the dimensions of an IC imply the weaknesses of the effects that raise when the dimension of the circuit is comparable with the atomic dimensions.

  56. etnapowers
    August 4, 2014

    Agreed, the increased integration causes many challenges in the heat dissipation caused by static and dynamic power consumption

  57. etnapowers
    August 4, 2014

    @jim: the length of the ground path influences the parasitic inductance but the width influences the parasitic capacitance so I think that the optimum value in terms of form factor has to be found to avoid ESD disruptive discharge.

  58. etnapowers
    August 4, 2014

    The presence of lower capacities and of high speed diodes is a guarantee of increased impedance and decreased charging time, I think that it is a good feature, provided the long term reliability of the capacitors and their robustness to voltage peaks for many cycles are both good

  59. jim_colby
    August 4, 2014

    It will certainly be satisfying if the market does realize the upside potential!  Forecasting existing markets can have a pretty wide margin of error, so it will be interesting to see how close these sources are.

  60. Davidled
    August 4, 2014

    The component market share could be the double over the next five years and hit more than $12B. Since it indicates that there is a huge market in the mobile sector, company needs to implement a decent process with design and validation for circuit protection.  

  61. Netcrawl
    August 5, 2014

    @Daej I agree with you, most of the growth are coming from Asia, especially where we seen a massive explosion in the mobile industry. The problem here is the quality and design process, its quite different in asia's world, they have these different taste and culture. 

  62. jim_colby
    August 5, 2014

    Yes, you are correct.  The inductance will act as a choke for the ESD transient (and degrade the protection performance) and the parasitic capacitance will act to degrade high speed signal performance.  Our recommendation is to not only minimze the length/width of the stub trace, but to eliminate it if possible.  For the connection to the data/signal line, place the solder pad right on/adjacent to the trace if possible.  This can be done for discrete diodes as well as a number of arrays that are designed to be placed right over the data tracks.

    This is one reason that we suggest to consider the boardl-level ESD protection approach as early as is possible or reasonable.

  63. etnapowers
    August 6, 2014

    “This is one reason that we suggest to consider the boardl-level ESD protection approach as early as is possible or reasonable.”

     

    @Jim: I fully agree with you, the design of the layout of a board that is well protected from ESD is the result of experience and a good balance of all the factors that can help to avoid the electrostatic discharge event or at least limit its damages.

  64. jim_colby
    August 6, 2014

    @etnapowers;  Thanks for comments.  We find this to be a very challenging aspect to protecting new applications.  We certainly understand that our devices do not add to the “value” of our customers products, nor do they increase the capabilities of the application.  So, they are typically considered at the end of the design process when EMC testing comes due.  However, board level ESD protection does help to ensure that these incredible new devices are able to reliably fulfill their functions and for their inteneded lifetimes.

  65. etnapowers
    August 6, 2014

    @Jim: I think that the design strategy of ESD protection should be an important step of the design of the PCB. The robustness of a circuit to the ESD discharges is directly correlated to the long term reliability, from the customer point of view this is a guarantee of quality.

  66. Davidled
    August 10, 2014

    Engineer might build basic electronics circuit standards, wearable module standards, and then the detailed standards such as applied sensor. Designer will go through three level processes and then produce more reliable products. The content of each standard will be implemented in the company committee. Therefore, each company might have a little bit different standard level.

  67. samicksha
    August 15, 2014

    I see your point @Sunita, but i believe in case of bidirectional we need to have voltage levels both above and below the reference voltage,usually ground and from recent findings lot depends on the properties of the circuit being protected.

  68. fasmicro
    September 9, 2014

    >> Forecasting existing markets can have a pretty wide margin of error, so it will be interesting to see how close these sources are.

    They do rely as everyone relies on them. VCs depend on those numbers to allocate capital. Even the companies look at those numbers. It is a social science and never science.

  69. goafrit2
    September 9, 2014

    >> the advantages of reducing the dimensions of an IC imply the weaknesses of the effects that raise when the dimension of the circuit is comparable with the atomic dimensions.

    Apparently you wanted to say Feture Size of transistors. It will take a long time for the dimension of a decent circuit with pads to get into the atomic dimensions.

  70. goafrit2
    September 9, 2014

    >> Agreed, the increased integration causes many challenges in the heat dissipation caused by static and dynamic power consumption 

    That is the reason why it makes sense to think through if a design can be optimally made in a 0.5um process or go down in the nanometer CMOS process. There are many MEMS products you can do effectively in 0.5um and avoid the troubles of static power dissipation.

  71. etnapowers
    October 6, 2014

    Some very new substrates, like the graphene , might reduce the time for achieving this result. 

  72. etnapowers
    October 6, 2014

    @goafrit2: That's for sure a consideration that I consider very useful during the feasibility analysis and start up phase of a project, considering all the constraints, among which the static and dynamic power consumption.

  73. fasmicro
    October 7, 2014

    >> Some very new substrates, like the graphene , might reduce the time for achieving this result. 

    We have all expected that to have happened by now but it seems the process is taking longer.

  74. fasmicro
    October 7, 2014

    >> considering all the constraints, among which the static and dynamic power consumption.

    Dynamic power is a big issue but when the static power becomes huge, we have a real problem as it takes away the vital advantage that CMOS offers besides the integration density over BJT

  75. etnapowers
    October 7, 2014

    I think that it's taking some more time than the prevision, you're right, but I think that it's important to explore the possibilities offered by this new  material as well. Graphene might be a revolutionary material to be utilized for the ICs  which promises a tremendous level of integration.

  76. etnapowers
    October 7, 2014

    That's absolutely true. I think that it depends on the particular situation, sometimes the static power dissipation might be reduced by a smart power management of the circuit, if this is not possible I agree with you on the CMOS that is really a good solution because the static power dissipation is very low.  

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