3D Stacking Offers New Path to Optimum Integrated Analog Performance

Designers, who need to build high performance real-time sensing systems, are greatly challenged since every building block in the system needs to be built with a technology that allows that building block to achieve its best performance. 3D stacking is emerging as an option to allow the integration of those heterogeneous blocks.

In general, technologies like BJT and BiCMOS are better suited for building basic analog blocks like input buffers and power amplifiers, while CMOS is the best choice for digital data processing. For the construction of mixed-technology systems, system-in-package (SiP) techniques have traditionally been used. SiP integration uses bonding wires or flip chip instead of on-chip integration.

However, exciting new research opens the door to the use of 3D stacking to integrate heterogeneous blocks built using different technologies in such systems.

Design methodology

Figure 1

Basic building blocks for data acquisition systems

Basic building blocks for data acquisition systems

Figure 1 shows a system that was evaluated in a study done at the University of Southern California (see below for additional details). The main analog blocks of the data acquisition system are the input buffer and the analog to digital data converter. In high speed and high throughput systems, like radar and real time oscilloscopes, the input signal arriving at the analog front-end usually has a bandwidth in multi GHz. Handling such high-speed signals requires high-speed buffers and fast data converters. The data is then fed to a back-end digital system for further processing. It was assumed that there is sufficient digital processing capability and hence the study focused only on the analog front-end. The accuracy of the overall sensing system depends on the quality of the data provided by the analog front-end.

Three options for system integration were explored in this study. The first option is that the two blocks, the input buffers, and the ADCs are integrated using bonding wires. The second option is to use the flip chip and the silicon interposer to integrate multiple dies together; for simplicity this design is simply called a flip chip.

The third option integrates the two blocks using through silicon vias (TSVs) into a 3D stack. In order to accurately quantify the cost-benefit analysis of 3D integration versus off-chip bonding, the wire parasitic was modeled.

Some previous studies on 3D stacking focused on integrating multiple digital blocks and using TSVs to transfer digital signals between the layers in a stack. The behavior of the analog signals traversing through TSVs and measuring how well 3D stacking can enhance or limit the performance of analog and digital stacking is critical to their effective use in such a design.

In order to examine and quantify the power and performance characteristics, we can model bonding wire, flip chip, and TSV interfaces. In the simulation experiments, a comparison was done for the three configurations under study — bonding wires, flip chip, and TSVs — to combine the CMOS input buffer with the ADC. The results were compared in terms of supported bandwidth, power consumption, area overhead, and signal integrity.

Using these models, it has been shown that 3D stacking of analog and analog/digital components can double the bandwidth, increase sampling frequency by nearly two orders of magnitude, and improve the signal integrity by 3 dB compared to bond wires.

For additional information and details from this 2012 study, please refer to “A Case for 3D Stacked Analog Circuits in High-Speed Sensing Systems,” written by Mohammad Abdel-Majeed, Mike Chen, and Murali Annavaram of the Electrical Engineering Department, the University of Southern California, Los Angeles.

Please give us your inputs and experiences in this critical area of design enhancement by means of analog integration techniques that you may have found useful.

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