3D Stacking Offers New Path to Optimum Integrated Analog Performance

Designers, who need to build high performance real-time sensing systems, are greatly challenged since every building block in the system needs to be built with a technology that allows that building block to achieve its best performance. 3D stacking is emerging as an option to allow the integration of those heterogeneous blocks.

In general, technologies like BJT and BiCMOS are better suited for building basic analog blocks like input buffers and power amplifiers, while CMOS is the best choice for digital data processing. For the construction of mixed-technology systems, system-in-package (SiP) techniques have traditionally been used. SiP integration uses bonding wires or flip chip instead of on-chip integration.

However, exciting new research opens the door to the use of 3D stacking to integrate heterogeneous blocks built using different technologies in such systems.

Design methodology

Figure 1

Basic building blocks for data acquisition systems

Basic building blocks for data acquisition systems

Figure 1 shows a system that was evaluated in a study done at the University of Southern California (see below for additional details). The main analog blocks of the data acquisition system are the input buffer and the analog to digital data converter. In high speed and high throughput systems, like radar and real time oscilloscopes, the input signal arriving at the analog front-end usually has a bandwidth in multi GHz. Handling such high-speed signals requires high-speed buffers and fast data converters. The data is then fed to a back-end digital system for further processing. It was assumed that there is sufficient digital processing capability and hence the study focused only on the analog front-end. The accuracy of the overall sensing system depends on the quality of the data provided by the analog front-end.

Three options for system integration were explored in this study. The first option is that the two blocks, the input buffers, and the ADCs are integrated using bonding wires. The second option is to use the flip chip and the silicon interposer to integrate multiple dies together; for simplicity this design is simply called a flip chip.

The third option integrates the two blocks using through silicon vias (TSVs) into a 3D stack. In order to accurately quantify the cost-benefit analysis of 3D integration versus off-chip bonding, the wire parasitic was modeled.

Some previous studies on 3D stacking focused on integrating multiple digital blocks and using TSVs to transfer digital signals between the layers in a stack. The behavior of the analog signals traversing through TSVs and measuring how well 3D stacking can enhance or limit the performance of analog and digital stacking is critical to their effective use in such a design.

In order to examine and quantify the power and performance characteristics, we can model bonding wire, flip chip, and TSV interfaces. In the simulation experiments, a comparison was done for the three configurations under study — bonding wires, flip chip, and TSVs — to combine the CMOS input buffer with the ADC. The results were compared in terms of supported bandwidth, power consumption, area overhead, and signal integrity.

Using these models, it has been shown that 3D stacking of analog and analog/digital components can double the bandwidth, increase sampling frequency by nearly two orders of magnitude, and improve the signal integrity by 3 dB compared to bond wires.

For additional information and details from this 2012 study, please refer to “A Case for 3D Stacked Analog Circuits in High-Speed Sensing Systems,” written by Mohammad Abdel-Majeed, Mike Chen, and Murali Annavaram of the Electrical Engineering Department, the University of Southern California, Los Angeles.

Please give us your inputs and experiences in this critical area of design enhancement by means of analog integration techniques that you may have found useful.

26 comments on “3D Stacking Offers New Path to Optimum Integrated Analog Performance

  1. Brad Albing
    May 23, 2013

    I've seen the term “flip chip” before, tho' have not had a good understanding of it. Can you explain what exactly is a flip chip?

  2. Steve Taranovich
    May 23, 2013

    A flip chip is a chip packaging technique in which the active area of the chip is “flipped over” facing downward. Instead of facing up and bonded to the package leads with wires from the outside edges of the chip, any surface area of the flip chip can be used for interconnection, which is typically done through metal bumps of solder, copper or nickel/gold. These “bumps” or “balls” are soldered onto the package substrate or the circuit board itself and underfilled with epoxy. The flip chip allows for a large number of interconnects with shorter distances than wire, which greatly reduces inductance.

  3. eafpres
    May 23, 2013

    FYI, flip chip assembly has been widely used in RFID tags to attach the tiny chip with the memory and control to respond when pinged.  The main driver there is ultra-low cost–you flip chip attach the chip right to the “antenna” which is either a flexible printed circuit or even a cheaper approach like metal foil on paper.

  4. eafpres
    May 23, 2013

    Hi Steve–very interesting stuff.  I'm a follower of the technology for senosors, in part because I'm watching the evolution of the Internet of Things which as I've noted elsewhere depends at the lowest level on deployment of billions of sensors, which are almost all inherently analog.  So the integration of ADC into higher level packages is a critical part of the chain to measure all those things before the data get onto the internet.

    I'm dimly aware that 3D is the roadmap for high performance processors.  There, there are tradeoffs of potential performance vs. thermal issues.  The more density that is obtained, and 3D using TSV should be inherently higher density, the more thermal problems you have.

    Do you have any thoughts on the commercial roadmap for integrated devices as you describe, and if such parts may eventually require thermal solutions like todays processors do (i.e., thermal gap pad to a heat sink or some such solution)?

  5. bjcoppa
    May 23, 2013

    3D stacking or 3D-ICs are an emerging trend that is here to stay. It simply makes sense to pursue that direction from a fundamental perspective. Analog ICs are slower in developing that tech than logic and memory companies which are highly sensitive to power consumption in mobile ICs that have been driving the industry the last couple years. Samsung just released a 45nm memory on logic chip stacked device and others like Nvidia are seeking to stack graphics chips with logic etc. 

  6. Brad Albing
    May 23, 2013

    OK – makes sense. I see how that can reduce cost and improve performance at high to super high frequencies.

  7. Brad Albing
    May 23, 2013

    Hmm… foil on paper – that will surely take some of the cost out. Not very rugged, but for security tags on clothing (e.g.), pro'ly good enough.

  8. eafpres
    May 23, 2013

    Yep.  You can find these tags in various high-value items like electronics packaging. Some are made like a peel & stick label.  If you think this through, then it starts to make sense that Avery-Dennison is a leader in RFID item-level tags.

  9. Steve Taranovich
    May 23, 2013

    I think that most integrated analog will be done in low power CMOS which is capable of most analog and digital functions. Typically the power elements are off-board and mounted separately on the pc board as you are aware.

    In the case of better thermal management, I am a fan of synthetic diamond for future IC designs if heat needs to be removed efficiently. When people hear the word “diamond”, they think high price, but the excellent thermal conduction of synthetic diamond is so efficient in conducting the heat away from the IC to the board, that it may well be more cost-effective than other methods, plus the cost of synthetic diamond will probably come down in the future.

  10. Steve Taranovich
    May 23, 2013

    You are absolutely correct, eafpres—known as RFID, these devices are getting smaller, smarter and require essentially no power supply on board–see TI's website for more details and also Maxim's website

    May 23, 2013

    Flip chip is also called bumped die. The normal bonding pads for a die are slightly larger to accomodate the solder balls. There is typically a passivation layer in place before mounting the solder balls, if I recall.

    The technology has been around for at least 10 to 15 years. It is not until recently that it is becoming more widely used. Several MOSFET manufacturers, Vishay (MicroFoot) and IR to name two, have bumped die packages. This keeps circuit area to the minimum as one cannot get much smaller than the die itself.

    Brad, I will send you a jpg of what bumped die looks like for MOSFETs. I could not see how to paste the picture in on the reply. Feel free to post in as you may know how.

  12. Scott Elder
    May 23, 2013

    The real value in flip chip is in how the ICs are made.  

    Rather than taking a wafer and then partial testing, slicing, mounting, bonding, encapsulating, lead trimming, and then full testing; one can take the whole wafer, drop on a bunch of solder balls, throw on some plastic across the wafer back, test the whole wafer once in parallel with multisite testers (i.e. 32 at a time), then slice and put on tape and reel.  Very very cheap.  Maybe two orders of magnitude less materials.

    No gold bondwires, no multi cycle testing, no large packages and lead frames, etc.

    The problem is moved to the PCB assembler who must figure out how to flow solder under the ICs where the balls are 350um apart.

    Here is a little factoid most board designers haven't thought about when using those WLCSP packages.  LIGHT REFLECTION!!!

    The backside of a CSP is not sealed.  Light can reflect off the PCB traces and into the IC circuit nodes under the die.  And light is current.  And IC currents are very small.  So precision circuits will start to fall apart (i.e. if you're trying to manage a low offset voltage on a precision op amp).

    I can just imagine the frustration sending parts called good back and forth till someone figures out the light reflection is killing the spec.

  13. Brad Albing
    May 23, 2013

    So, those parts can be called inexpensive -and cheap – with the negative connotations. I suppose the light-induced-leakage problem is understood at this point. so we can't play the part of savior consulant who miraculously solves the manufacturer's problems.

  14. Brad Albing
    May 23, 2013

    These parts are the ultra low power scavaging devices that we hinted at in this blog:

    We'll discuss more of these very low power devices later.

  15. Brad Albing
    May 23, 2013

    Thanks Derek. You can copy an image to the clipboard from (e.g.) MSWord and then just paste it into the text as your typing your message. Example:

    Or you can drag-and-drop an image file right in to the message window. Example:

    And grab on to a corner to adjust the image size.


  16. Steve Taranovich
    May 24, 2013

    Great observations Scott! I remember when Burr-Brown used the silicon Vbe junction sensitivity to photons to their advantage when the developed the OPT101 light-to-voltage converter

  17. Brad Albing
    May 24, 2013

    Is that the same synthetic diamond that grinding and cutoff wheels use? If so, then prices should indeed plummet once its used more in semiconductors.

  18. Steve Taranovich
    May 24, 2013

    Absolutely Brad—it's used for precision machining, drilling, crushing, sawing and milling. Check our Element Six website for details

  19. Brad Albing
    May 24, 2013

    Ah… element 6 – I get it.

  20. Brad Albing
    May 24, 2013

    I recall the OPT101. I used that in a design a bunch of years ago.

  21. amrutah
    May 25, 2013


       Thanks for the post.

       With Intel pushing the Moore's Law further by coming up with the Silicon photonics, its further going to help improve speeds.  It is going to change the IC's. I think this along with 3D stacking will help integrate a lot of solutions.  Any idea about the roadmap here?

  22. Steve Taranovich
    May 25, 2013

    Roadmaps depend upon who you talk to. A couple of examples I have seen are:

    NVIDIA is planning a stacked “stacked DRAM”, connected to the GPU with TSV, in an upcoming GPU that will allow access to up to one terabyte per second of bandwidth.

    Qualcomm is planning 3D through silicon via stacking (TSS) for a high-end smart phone application this year. They plan to start with Wide I/O DRAM on logic, then hybrid memory on logic, moving to logic on logic and then pretty much everything—no set timeframe given.

  23. Brad Albing
    May 28, 2013

    For those who've forgooten their high-school chemistry class:

  24. Brad Albing
    May 28, 2013

    >>…access to up to one terabyte per second of bandwidth. Yow! That will be interesting to see, purely from the point of view of the data link running at that speed.

  25. Steve Taranovich
    May 28, 2013

    That's right Brad—Carbon—put it under a million pounds of pressure for a million years and Voila!–a Diamond! It's essentially prehistoric plant matter from millions of years ago—I'm not sure why women love it so much? 🙂

    Or just synthesize one like Element six does 🙂

  26. Brad Albing
    May 28, 2013

    I know that Superman can make them by squeezing lumps of coal – saw that on TV when I was a kid. Seems educational, so I think it was on PBS.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.