8-bit ADCs proclaim 6 GSPS performance standard

Santa Clara, Calif.&#8212National Semiconductor's new 8-bit analog-to-digital converter (ADC) family touts a new performance standard for sampling speed&#8212 up to 6 gigasamples per second (GSPS) data capture at 3.6 watts.

The company's ADC083000, one of three new releases, operates at 3 GSPS and can be interleaved in a pair for 6 GSPS data capture without additional clock adjustment circuitry. Claimed best-in-class features include a full-power input bandwidth of 3 GHz, superior dynamic performance and low power consumption of 1.8 watts. The second product, the ADC082500, is capable of sampling speeds up to 2.5 GSPS, and the company's ADC08B3000 combines 3 GSPS sampling and a programmable 4 kbyte memory buffer. The ADC083000 and ADC082500 are suited for communications and test and measurement applications. The ADC08B3000 is suited for ranging applications such as RADAR and LIDAR (light detecting and ranging), where the data is captured in bursts and transferred at lower, more manageable data rates. All ADCs cite use of a unique folding/interpolation architecture to reduce the number of comparators and greatly reduce the number of front-end amplifiers to save power and reduce input signal loading.

The ADC083000 can digitize an input signal into 8 bits at sampling speeds up to 3 GSPS. It provides a 3 GHz full-power bandwidth, allowing for sampling of wideband signals even in the second Nyquist band. It has an adjustable sampling clock phase that allows designers to interleave multiple ADCs on a board without using costly, external clock-adjustment circuits. The converter offers 1:4 de-multiplexed outputs standard for simplified data capture or a new 1:2 output mode for reduced pin count when interfacing with an application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA). Both of these output modes use low-voltage differential signaling (LVDS).

The ADC083000 also has test patterns on the outputs for easier system design and test. A three-wire serial bus controls these features, as well as on-chip functionality, and gain and offset fine-tuning for the input. The ADC083000 typically achieves 7.0 effective number of bits (ENOB), 44 dB signal-to-noise ratio (SNR) and 54 dB spurious free dynamic range (SFDR) when sampling a 750 MHz input at 3 GSPS.

The ADC082500 is a 2.5 GSPS version of the ADC083000. The ADC08B3000, with the same performance specs as the ADC083000, is suited to data acquisition for applications where signal pulses need to be captured at gigasample speeds while processed at much slower rates. The ADC08B3000 samples one input at speeds up to 3 GSPS and stores the data in a 4K byte first in, first out (FIFO) memory buffer. One or two 8-bit CMOS output buses then transfer data from the FIFO out of the ADC to the processor at slower rates of up to 400 megabytes per second.

Click here for the ADC083000's datasheet, here for the AD082500, and here for the ADC08B3000. All three ADCs will be available in January 2007. Samples are available now. The ADC083000 is priced at $523 each in 1,000-unit quantities. Click here for additional information, including how to order samples and evaluation boards.

National Semiconductor , 1-800-272-9959,

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