ANALOG DEVICES’ HIGH-SPEED CONVERTERS SET NEW POWER EFFICIENCY BENCHMARK FOR COMMUNICATIONS APPLICATIONS
NORWOOD, MAAnalog Devices, Inc. is introducing a family of high-speed 10- and 12-bit analog-to-digital converters (ADCs) targeted for broadband communications and wireless infrastructure applications, such as cable modem termination systems, third and fourth generation microcell and picocell base stations, and fixed point-to-point radios, where low power consumption is required to accommodate smaller form factors, but high-quality conversion performance cannot be sacrificed. The flagship device is a 12-bit, 250 million samples per second (MSPS) ADC that cuts power consumption by more than 40 percent, is available in a package 20 percent smaller than competitive ADCs, and maintains superior signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) at high intermediate frequencies (IFs).
“The AD9230 is the only 12-bit, 250-MSPS ADC that has been able to bring power consumption below the 500 mW threshold, thus increasing power efficiency, decreasing system size and minimizing thermal management costs—attributes which are extremely important for today’s high-performance wireless and wired applications,” said Kevin Kattmann, product line director, High Speed Signal Processing Group. “The AD9230, used in the transmit path of picocell or microcell base stations to optimize power amplifier linearization, also facilitates more rapid system deployment by enabling smaller-sized end-systems. In cable termination systems, growing demand for digital cable services is placing greater emphasis on bandwidth, calling for low-power ADCs that allow higher channel density.”
The 12-bit, 250-MSPS AD9230 is the flagship device in a family of pin-compatible, low-power converters being introduced today. The device operates from a single 1.8 volt supply, dissipates only 425 mW of power and is capable of maintaining excellent SNR (65.5 dBfs) and SFDR (82 dBc) with a 70-MHz input. The AD9230 features an on-chip reference and track-and-hold, two parallel low-voltage differential signaling (LVDS) output modes (ANSI-644 and IEEE 1596.3 reduced range link) to ease the interface to FPGAs, and a double data rate (DDR) mode which halves the number of parallel outputs required. The DDR, combined with the IEEE 1596.3 reduced range link LVDS option, further reduces power consumption to 385 mW.
To maximize system performance, the AD9230 can be used with ADI’s AD8368, AD8369 and AD8370 radio frequency (RF) variable gain amplifiers. The family includes the 12-bit AD9230 offered in three speed grades (250 MSPS, 210 MSPS, 170 MSPS) and the 10-bit AD9211 also offered in three speed grades (250 MSPS, 200 MSPS, 170 MSPS).
Analog Devices, Inc. (ADI) puts a lot of muscle behind its converter product lines, and the new AD9230 is one example of how the company has pushed the performance envelope lately. The AD9230 analog to digital (A/D) converter is designed to bring greater efficiencies to wireless infrastructure and reduced power consumption and footprint to cable applications. It demonstrates specifications of 65.5 dBfs signal to noise ratio (SNR) and 425 mW power dissipation while handling 250 MSamples/s. And, particularly important for cable applications, with the 170 MSamples/s version, power dissipation drops to 350 mW.
“For wireless applications, the AD9230 is designed to address concerns from our customers about implementing PA pre-distortion schemes over a wider signal bandwidth which requires sampling rates up to 245 MSamples/s for 3G, 3.5G, and WiMAX applications,” explained Jon Hall, strategic marketing manager, high-speed converters group. “In these systems, implementing these digital efficiency techniques reduces the overall transmit sub-system cost and allows system providers to differentiate themselves in the marketplace.”
So, the team at ADI ensured that the 12-bit AD9230 could achieve a 170/210/250 MSamples/s rate, and could demonstrate a spurious free dynamic range of 82 dBc at the highest sampling rate in order to support PA linearization.
Form factors are also becoming more important in wireless infrastructure applications; the latest WiMAX base station designs are smaller than their wireless infrastructure counterparts. In response to this, the team at ADI designed the AD9230 into an 8 x 8 mm 56-pin package.
For cable applications, the AD9230 was optimized for power as well as size, “because a key consideration here is the ability to put more devices on a single printed circuit board in order to support future channel growth,” said Hall. For cable applications, the team also worked to provide good SNR performance (65.5 dBfs at 70 MHz) in order to satisfy DOCSIS requirements.
By far, one of the most impressive achievements of this device is its power dissipation, which is 425 mW at top sampling rates, and ADI reports that this is 43% less than what's on the market or announced today.
The AD9230 is not a first generation product, but it grew out of the company's AD9430, a 12-b 210 MSample/s device announced in 2002. The design team at ADI began work on the AD9230 in response to customer demand for a faster A/D converter in order to digitize a wide band of signals to implement predistortion techniques and ultimately improve the efficiency of the PA, particularly in 3G wireless systems. For wired broadband, customers needed a faster A/D in order to support digital telephony, as upstream or reverse-path cable traffic began to engulf the available bandwidth. In the case of cable applications, the AD9230 would typically be used in the Cable Modem Termination System (CMTS), where heat dissipation is an ongoing design challenge. Therefore, optimizing power consumption became critical for success in this application.
So, what design challenges did the team have to overcome? The AD9430 released in 2002 was manufactured using a BiCMOS process, which enables fast linear blocks in the first stage of the converter. The AD9230, however, was designed on a 0.18 CMOS process, so the team was forced to develop some inventive design techniques to handle the input frequency at a fast sample rate. While CMOS allowed the team to drive down power consumption, the challenge was to maintain first-stage linearity. While Hall would not reveal any secrets here, he did report that a lot of intellectual property (IP) was developed with this design.
If you are interested in this product, it will begin sampling in May 2006, with production scheduled to begin in September 2006. The 12-bit AD9230 is priced at $59 (250-MSPS), $47 (210-MSPS) and $35 (170-MSPS) in 1,000 qty.
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Analog Devices, Inc., +1 800-262-5643, www.analog.com .