A Planet Analog Primer: A Clock For Every Timing Need

Although system timing creates no differentiation at the product level, as the world shifts from parallel to serial connections, timing requirements are becoming more critical than ever. A large variety of clock chips are available on the market to address these needs. While this rich selection offers more flexibility in designing clock trees, the sheer number of possibilities may overwhelm inexperienced engineers. Adding to this confusion, system timing remains one of the least understood disciplines in hardware design.

To clarify the various clock options available to designers, this article attempts to classify the clock chip market into a few basic categories. The characteristic features of each category are examined to assist designers in matching their application needs to the specific type of clock that fills it. The intent is to help designers make better clock choices, leading to more efficient and cost-effective clock tree designs.

The mass of clock chips on the market can be categorized into the three main purposes that they serve. Figure 1 identifies these purposes as being to (1) create, (2) distribute, and (3) process clock waveforms. Because many chips are sold serving more than one purpose, a hybrid category is also shown. However, reducing any particular chip into its core purpose(s) may help to recognize the benefit(s) it provides. Figure 2 shows an example of how these categories may be combined to create a clock tree. Many other combinations are possible.

Figure 1 Clock chips may be categorized according to the function they serve. They are used to create a new frequency (clock creation), distribute multiple copies of a frequency (clock distribution), or process the input clock in some manner (clock processing). Hybrid clocks provide a mixture of these functions.

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Figure 2 Example clock tree showing one possible combination of creation (C), distribution (D), and processing (P) clock chips.

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Clock Creation

This category of clocks is concerned with creating one or more new clock frequencies. A clock chip from this category placed at the start of a clock tree is called a clock generator. Generators are needed to create the various clock frequencies required by the system. Alternatively, when a clock chip from this category is inserted inside a clock tree, referred to as an “in-line” application, it is called a clock synthesizer. If a generator is unable to create all required frequencies from the start, synthesizers can be used in the clock tree branches to fill out the rest of the frequencies.

Generic clock creation devices are illustrated in Figure 3. These devices are characterized by having output frequencies that are a multiple of the input frequency f1, where x, y, or z is any number (integer or non-integer). Clock generators, located at the start of the clock tree, require an oscillator source, such as a crystal, as an input. These chips have an internal oscillator to complete the required oscillation circuit. Aside from this input difference, generators and synthesizers are similar.

An internal phase-locked loop (PLL) forms the heart of these devices. The PLL translates an input frequency to the desired output frequency. If multiple simultaneous output frequencies are needed, dividers are placed in the output paths to create the required frequencies. In this case, the output frequencies are related by the divider values used. If multiple output frequencies are desired that are non-integer related, the generator must include multiple PLLs.

Chips targeting clock synthesizer applications may also provide an added benefit of level translation, including both signaling as well as voltage-level translation. For example, a chip may accept LVTTL inputs, and output LVPECL. The large number of signaling standards in the industry assures a large number of required translations. Similarly, the reference input or core supply voltage may be different than the output supply voltage. For example, a 5V LVCMOS input may connect to a chip with a core supply at 3.3V, and an output supply of 2.5V, to output 2.5V LVCMOS.

Clock Distribution

Clock distribution devices exist to provide multiple copies of one or more output frequencies. These devices are loosely referred to as “buffers” in the industry. This category may be subdivided into non-PLL versus PLL-based buffers, as illustrated in Figure 3. Without output dividers, non-PLL buffers simply provide multiple copies of the input frequency. If dividers are placed on the outputs, multiple frequencies can be output simultaneously. Typically, only integer division (N) is available in non-PLL based buffers. Because they do not contain PLLs, these devices cannot multiply the input frequency.

A cross-point switch / multiplex (MUX) is a special type of non-PLL based buffer used in applications where the inputs need to be switched. Figure 3 illustrates the variety of operations performed by this device. Two inputs connect to two outputs as either a (a) 1:1 buffer, (b) switch, or (c,d) 1:2 buffer.

PLL-based buffers enable multiplication (M) of the input frequency. Output dividers (N) may also be included to offer some division capability. These M and N values are generally integers. Fractional-N dividers are possible, but such specialized functionality is generally found in clock creation chips.

Besides multiplication, PLL-based buffers offer several other benefits compared to non-PLL based buffers. Since most PLLs operate on the rising clock edge input (not the falling edge), the input duty cycle can degrade significantly without degrading the output duty cycle. It's not unusual for such devices to accept input duty cycles down to 30 percent/70 percent or less. PLL-based buffers are therefore used wherever duty-cycle correction is required.

Figure 3 Illustrations of generic clock categories.

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Another benefit of PLLs is low input-to-output propagation delay. Sometimes referred to as “zero-delay buffers,” or ZDBs, the propagation delay can be reduced from nanoseconds for non-PLL based devices to hundreds of picoseconds for PLL-based devices. With near-zero propagation delay, the outputs appear phase synchronized to the inputs. A ZDB is therefore used for creating multiple outputs while adding negligible delay. Common clock bus architectures, which depend on synchronized clocks, are a popular application for ZDBs.

PLL-based clocks are also used to provide adjustable input-to-output delay. This application requires the PLL's feedback connection to be brought out to an external pin on the package. Introducing time delay on this feedback input allows one to control the input-to-output clock phase alignment. One way to create delay is to use capacitive loading. This may be achieved, for example, by connecting this pin to another chip, or by introducing a discrete capacitor. Ultimately, the loading on this feedback pin relative to the loading on the other output pins determines the advancement (more loading) or delay (less loading) between the reference input and the output clock edges. If the loading is equal, the device acts as a ZDB as described above.

The advantage of this approach is that board layout is relatively easy, and, in the case of the discrete capacitor, the load may be changed after the PCB is fabricated. The disadvantage is the capacitive load on the feedback input slows the edge-rate down, which increases jitter. A preferred approach to adjusting input-to-output delay is to use a transmission-line trace in the feedback path, where the transmission-line length is chosen to provide the desired amount of delay/advancement between input and output pins. Because this method maintains the edge-rate, the added jitter is minimized. Some chips include an adjustable internal delay feature, which the user can select for each output. In this way, PCB trace-length matching for board de-skewing can be achieved by configuring such a buffer with the appropriate delay for each output.

Another useful benefit of PLLs is their ability to attenuate jitter. The closed-loop nature of PLLs results in these buffers having bandwidths of a few MHz or less. Any jitter frequencies above this bandwidth are attenuated by the PLL. Thus, PLL-based buffers are natural jitter filters. Such devices are useful in applications where clock jitter is unacceptable and requires cleaning up. Lower bandwidth devices reach further into the lower frequencies to attenuate more jitter. However, lower bandwidth PLLs have larger time constants, which reduces the PLL's ability to track input frequency variations. This results in more intrinsic jitter added by the PLL. Therefore, depending on the magnitude of the input jitter, lowering the PLL bandwidth below a certain point may introduce more jitter than what it removes from the input.

In addition to the above benefits for clock distribution chips, these chips may also provide signaling and voltage-level translation, as discussed earlier for clock synthesizers.

Clock Processing

A third category of clock chips exists, whose purpose is neither to create nor distribute clocks. Figure 3 shows this clock category's purpose is to process the input clock waveform in some fashion. Such “task-oriented” clocks have a specialized function, which may serve any number of purposes. The simplest form may be a signaling-level translator. For example, chips are sold that simply take in LVTTL and output LVPECL. Variations exist covering most popular signaling standards.

More complicated forms include specialized PLL-based jitter attenuation devices. Such devices may comply with industry specifications (i.e. SONET) for jitter generation and jitter peaking. Chips sold to enable clock redundancy represent another variety of clock processor. These chips have two (redundant) inputs, such that if the chip detects that one input dies, the output phase and frequency switch smoothly to the other input.

Spread-spectrum clock generation (SSCG) is another type of clock processor, which is widely used to reduce system electromagnetic interference (EMI). These SSCG chips output a frequency-modulated version of the input reference frequency. This scheme reduces system EMI by smearing, or spreading, the output frequencies over some limited range, which is usually less than 1% of the input frequency. Because the output clock waveform is spread over a range of frequencies, the power present in any one frequency in the output signal is reduced compared to the power present at the single input frequency. Doing this improves signal integrity within the board.

Hybrid Clocks

Hybrid clocks include combinations of clock creation, generation, and processing features. Figure 3 illustrates one possibility, which may include SSCG, clock synthesis with an in-line input or clock generation using an alternate (crystal) input, plus some clock distribution capability. Many varieties of hybrid clocks are available in the market. In fact, market forces are shaping clocks to become more application specific. The effect of tailoring clocks to their specific end-market tends to favor the creation of hybrid clocks. For example, the PCI market requires SSCG with 1% down spread, so this is usually built into clock generators targeting PCI output frequencies.

Picking The Right Clock For The Application

With clock chips categorized by purpose, let's examine their key differentiating features to help select the most appropriate category for the application. Table 1 summarizes these key differentiators. As discussed earlier, any PLL-based clock corrects for poor input duty cycle. Generators, synthesizers, and PLL-based buffers therefore provide this benefit. If the application simply requires translating the I/O signaling standard and/or voltage levels, non-PLL buffers are the smallest, most cost-effective solutions. However, synthesizers and PLL-based buffers also provide these translations, and serve dual purposes when other features are needed.

Jitter attenuation is a natural by-product of the (relatively) narrow bandwidth inherent in PLL-based devices. Although a variety of clock processor chips are sold specifically for this purpose, they can be somewhat expensive since they are specialized chips whose performance complies with industry standard specifications. If the level of attenuation needed is not critical, an inexpensive solution can usually be achieved by selecting general-purpose synthesizers or PLL-based buffers having the smallest bandwidth possible.

When it comes to creating a new output frequency, there are many options. The simplest, most inexpensive, is a non-PLL buffer equipped with output dividers. Obviously, this solution only divides the input frequency. Also, the dividers are usually just integers, so the number of possible output frequencies is quite limited. To multiply the input frequency, a PLL is required. If the input frequency comes from a crystal, a generator is the obvious solution. However, since crystals can typically only create frequencies up to 30 MHz, generators have a limited input frequency range. Applications requiring larger input frequencies must choose synthesizers or PLL-based buffers. If the input-to-output frequency ratio is integer related, PLL buffers are generally selected because many options are available that multiply the input frequency plus offer some distribution capability. Synthesizers are popular when this frequency ratio is non-integer.

Table 1. Typical Differentiating Features Between Clock Categories.

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If multiple output frequencies are needed where the output frequencies are non-integer related, clock creation devices are the best choice. These devices include multiple PLLs, each one providing a unique output frequency. However, if the multiple output frequencies are integer related, clock distribution chips may provide a simpler, more cost-effective alternative.

Applications needing to distribute clocks while preserving the original phase position require PLL-based buffers. These buffers must be configured in a zero-delay configuration, meaning an output must be connected back to the PLL's feedback input. Sometimes this is done internal to the clock chip. Other times, an external pin is available for delay compensation. If a transmission line is connected to this pin, the delay of the transmission line is eliminated by the PLL's feedback loop. If the rest of the outputs have a similar transmission line (i.e. length) attached to them, their outputs are then phase synchronized to the input. In this way multiple copies are created with near-zero delay with respect to the input waveform. If a capacitive load or transmission line is placed between a clock output and the feedback input pin, the rest of the outputs may be delayed or advanced with respect to the input as described earlier.

Clock processor chips are available to perform a variety of tasks. The few examples mentioned above are listed in Table 1. There is also a wide selection of hybrid clocks available. Looking at Table 1, hybrid clocks exist for each row containing features from multiple categories. Of course, variations of hybrid clocks extend well beyond the possibilities summarized in Table 1.

Key Specifications to Evaluate

Because each clock category serves a different purpose, it's important to understand what qualities to look for when choosing clocks within each category. Table 2 highlights some of the key performance specifications that should be evaluated in choosing the most appropriate clock for the application. In general, devices having the lowest specification number, for specifications identified in Table 2, achieve the best performance. However, the best performance may not always be the best solution, since performance comes with a price.

Table 2 Key Specifications to Evaluate When Selecting Clock Chips.

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The amount of jitter any chip adds is almost always a critical performance specification. Since clock creation devices are typically close to the original oscillator source, key parameters include frequency accuracy and stability. The ppm numbers for these specifications are dominated by the oscillation source, such as the crystal attached to the chip. However, any fractional-type divider used to create a new frequency can introduce additional degradation.

Clock distribution buffers, since they provide multiple copies of the input, have an output-to-output skew specification defining how far apart rising edges between any two output waveforms can be. PLL-based buffers used in zero-delay configurations also have an input-to-output propagation delay figure-of-merit. Obviously, the lower this delay, the more “zero-like” delay the chip provides. In cases where a controlled input-to-output delay is desired, PLL-based buffers with programmable internal delay are available. These buffers will have some maximum amount of possible delay, as well as some minimum adjustable delay step size. Smaller delays provide finer de-skewing adjustments, which increases the timing margin available to the designer.

Programmable Clocks

While adding programmable features to a clock chip does not change the inherent purpose, or category, of the clock chip itself, it does offer several additional benefits designers should be aware of when selecting clock chips. For instance, in the race to ship systems complying with the latest standards, programmable chips allow designers to tweak the system's clock features without redesigning the board, which speeds time to market.

Companies also buy programmable clocks to consolidate their inventory. Instead of buying multiple products to support a variety of frequencies, for example, one chip is bought, qualified, and stored in inventory. This streamlines the manufacturing process, saving cost. The next time a clock chip is required for a new design, the programmable clock, which is already qualified and proven in past designs, may be used.

Programmability in otherwise pad-limited chips provides the added benefit of smaller package footprint (fewer pins). Without programmability, pins would need to be biased to select the desired feature set. Depending on the number of features available, the final pin count may be reduced significantly by making such features programmable. The tradeoff, of course, in having programmable chips, is the overhead needed to program them. Therefore, systems already having serial interfaces, via ASICs, FPGAs, or other controllers, are a natural fit for including programmable chips. Some varieties of clock chips may also be programmed using EPROM registers.

The Choice Is Yours

With the huge selection of clock chips available to the designer, it's useful to step back and understand how the unique characteristics of each are best suited for the intended application. Use this guide to navigate your way through the sea of clock chips to create the most efficient and cost-effective clock tree design for your application.

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