Accelerating the time to mixed-signal IC layout requires a change in methodology

With the move to nanometre geometries, IC design is becoming considerably more complex and time consuming.  At the same time, analog content is increasing, reflecting strong growth in wireless and sensing technologies, and driven by the consumer, medical and automotive industries.  Market research indicates that although analog circuitry takes up only 20 percent of the area of today's modern mixed signal devices, it is likely to account for some 80 percent of yield loss.

The critical issues here are that due to the complexity of the design and the dramatic increase in process related design rules that have to be considered, mixed signal design, and especially full custom design, is leading to more errors and performance related problems.  Manual design and layout is no longer viable, yet automation in the analog design world remains difficult, and is often an anathema to analog designers.       

The quandary of the analog IC design bottleneck was the focus of a panel session at the recent GSA & IET International Semiconductor Forum, which took place in London in May 2010.  The Global Semiconductor Alliance together with the UK's Institution of Engineering & Technology joined forces to highlight and discuss European trends in semiconductor development.  This year's program focused on leveraging and maximising European expertise in analog/mixed-signal, wireless/portable, and low-power applications.    

The article, which originally appeared at the EE Times Europe-Analog web site, is available here .

About the author
Paul Double is EDA Solutions founder and CEO. After gaining a B.Sc. Hons. in
Physics and Electronics at the University of Warwick, UK, Double started his
career in IC Design with Phillips Semiconductors (now NXP), eventually
moving into product management.

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