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Accommodating DC-level mismatch in multi-gigabit serial data transmission

Background
AC coupling using a series capacitor is a simple method for coupling multi-gigabit transmitters and receivers. It requires only one inexpensive passive component and eliminates complications due to mismatched transmitter and receiver DC voltage levels. However, low-frequency cutoff limitations of AC coupling capacitors can limit system performance for random and long run-length encoded data.

Careful matching of transmitter and receiver common-mode voltages allows direct coupling of the transmitter and receiver, eliminating the need for AC coupling capacitors. When it is impossible to match the common-mode voltages, DC coupling of the transmitter and receiver can be realized by using voltage-leveling circuits. While voltage leveling circuits do add complexity to the circuit, DC coupling can enable significant improvements in system performance.

Signal distortions that may result from AC coupling
This paper describes the low-frequency components of long data patterns and the signal distortion that occurs from blocking these components. Other related issues, such as the effects of unbalanced high and low logic levels, (e.g., baseline wander and resulting bit errors) are also discussed. On the high frequency end of the spectrum, AC coupling capacitors exhibit self-resonance and begin to behave like inductors. However, the inductive reactance is actually quite small compared to the characteristic impedance (Z0 ) and the real problem is with lower frequencies.

Attenuation of the low-frequency portions of a serial data stream distorts the signal in ways that can be difficult to observe on a high-speed oscilloscope, but these distortions may cause bit errors. In a commonly observed example, a system may exhibit error-free performance with a 27 – 1 pseudorandom bit sequence (PRBS), but the same system may generate many errors when the test pattern is changed to a 231 – 1 PRBS, Figure 1 . The RC filtering effect of the coupling capacitor results in slow baseline fluctuations which induce zero-cross jitter. This jitter, although path and pattern dependent, appears almost random and is not readily compensated by transmit pre-emphasis or analog receive equalization techniques.


Figure 1: (Click on image to enlarge) 231 -1 PRBS Pattern Baseline Wander – (red) Integral of 1s and 0s showing long-term DC imbalance. (blue) 10k-bit 1/0 moving average. Note that the maximum DC imbalance is almost -12%.

Resistive Networks
The familiar pi or tee network, used to match unequal impedances, can be extended to shift DC levels while maintaining equal characteristic impedances, Figure 2 . This can work well if the DC mismatch is not large but it causes greater than 6 dB attenuation when the common mode voltage differs by more than a 3:2 ratio. In addition, the resistor network requires board space and additional attachment pads, both of which can degrade signal integrity at high data rates. Finally, the resistive matching network consumes a significant amount of power.


Figure 2: (Click on image to enlarge) Example of Resistive Common Mode Voltage Matching: This example shows interfacing between a Vitesse VSC3172 crosspoint switch and TMDS video I/Os. With the resistor values shown, the TMDS to VSC3172 network consumes an extra 32 mW per interface (double that for each differential port) and the signal is attenuated by 50%. The VSC3172 to TMDS network uses 21 mW and attenuates the signal by 40%.

Common Positive Supply Rail
Typically, CML outputs are referenced to the positive supply. When transmitters and receivers are powered with different voltages, the resulting DC common modes differ by about the same amount as their respective supplies. The signal common-mode voltages can be made identical by operating the devices from a common positive voltage supply with different negative supplies, Figure 3 .


Figure 3: (Click on image to enlarge) Reference Design for an HDMI Switch: A forward-biased diode is used to offset the board ground by +0.8V above chassis ground. This matches the HDMI Vcm with the 2.0 – 2.5V Vcm of the crosspoint switch. In this example, high-speed switching uses a Vitesse VSC3316 and low-speed and DC switching uses a Maxim MAX4814.

Series Diode
A third approach is to use a series diode in place of the AC coupling capacitor, Figure 4 . This is possible when the diode forward bias voltage is within the spread of the difference in DC common mode voltage. A small forward bias current, through a resistor to VCC, keeps the diode in conduction. This matches DC offset with no AC signal attenuation. It requires fewer components that a resistor network and, since the bias resistor is high resistance, does not affect signal integrity. Pre-emphasis and input equalization can function normally and complex run-length encoded or scrambled data do not degrade jitter as much as with AC coupling.


Figure 4: (Click on image to enlarge) Diode-based Vcm Matching: Vcm for 3.3V CML ranges from about ˜2.8 – 3.3V and ˜2.0 – 2.5V for 2.5V CML. An inline diode, biased through a 1 kO resistor, provides the voltage drop needed to match DC common mode voltages between the two logic groups. In this case, a Vitesse VSC3172 (2.5V CML) crosspoint switch is DC-coupled to a Video TMDS transmitter or receiver.

Conclusion
Each of these methods is quantitatively analyzed as well as validated with lab measurements of practical systems. Eye diagrams, jitter plots, and bit error ratio (BER) data are included to illustrate the effects of the different coupling methods on multi-gigabit systems that include lossy transmission lines and equalizers. Each method has its place depending on data rate, encoding complexity and DC common mode mismatch. For the most demanding combination of design constraints, we have shown that the biased series diode offers the best performance with minimal increase in complexity and power consumption

About the author
Eric Sweetman , Ph.D., is a Principal Engineer for the Serial Data Solutions Product group at Vitesse Semiconductor Corporation. Eric has worked in various research and development roles covering signal integrity, radio frequency identification (RFID) and Interconnect technologies. Prior to joining Vitesse in 2003, Eric held signal integrity & RFID R&D positions at Accelerant Networks and Lucent Technologies. Eric holds several patents in RFID technology. He holds a PhD and MS in physics from the University of Michigan and an SB in physics from MIT.

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