Accurate Circuit Verification of Integrated Power Switches

The Planet Analog post by Paul Illegems, “Can You Easily Build Integrated Power Switches? Part 2,” offers sound design principles to limit switch Rds_on and parasitic routing resistance when building integrated power switches. Following up with circuit verification is an important step to ensure design integrity through parasitic extraction and final simulations. Understanding and making the most of these tools to model parasitic metal and VIA resistance is important. It allows a designer to verify that a power switch will meet or exceed its design specification.

Power switches are often distributed into arrays of device fingers and VIAs with large metal routes to limit metal resistance. It may not be uncommon for this routing to include millions of VIAs spread throughout a number of metal layers. This can make it a challenge to develop a back-of-the-envelope simplified resistance model. Combining parasitic extraction and simulation tools harness a powerful means to model these parasitics. A designer should be cognizant that modeling accuracy is often compromised with the speed of parasitic extraction and simulation time. With the following recommendations, a designer may have a greater level of confidence in the accuracy of circuit verification for an integrated power switch.

Parasitic Extraction Tools

When utilizing a parasitic extraction tool to model routing resistance, a variety of VIA reduction techniques are offered to limit the size and complexity of its parasitic netlist. Care must be taken with the extraction tool not to oversimplify the equivalent parasitic circuit. For instance, consider the basic metal and VIA array network resistance from Point A to Point B in Figure 1:

Figure 1

Figure 1: 10 
Point A to Point B Equivalent Resistance

Figure 1: 10 Ω Point A to Point B Equivalent Resistance

The equivalent resistance from Point A to Point B in Figure 1 is 10 Ω . However, default VIA reduction techniques offered with parasitic extraction tools may combine these parallel VIAs into a “SuperVIA” located at the midpoint in the array. This VIA reduction technique illustrated in Figure 2 results in an equivalent resistance of 15 Ω :

Figure 2

Figure 2: 15
Point A to Point B Equivalent Resistance

Figure 2: 15 Ω Point A to Point B Equivalent Resistance

The basic VIA reduction example of Figure 2 yields a 50% difference in equivalent resistance compared to the actual network resistance of Figure 1. A designer must understand and carefully weigh the tradeoffs between accuracy and size of an equivalent parasitic netlist. For an integrated power switch utilizing millions of VIAs, the addition time required to create an accurate parasitic model may be necessary. Therefore, disabling VIA reductions during parasitic extraction is recommended.

Furthermore, parasitic extraction tools generally offer a minimum resistance threshold such that resistors smaller than a particular value may be ignored or reduced/simplified. Although this option is helpful to limit the size of parasitic netlists, this reduction comes with a sacrifice in accuracy. An integrated power switch will typically attempt to utilize wide metal tracks and large VIA arrays, resulting in very small resistances spread over a very large network. An accurate parasitic extraction will need to take into account this large number of very small resistances.

Simulation Tools

Likewise, when performing parasitic verification simulations on a power switch, advanced simulation tools offer the ability to ignore resistors below a minimum resistance threshold. Again, a designer should consider the tradeoff between accuracy and simulation speed. Small resistances spread over a large network may add up sufficiently to offset the accuracy of the simulation results. As a result, it is recommended to set a low (or 0 Ω ) minimum resistance threshold. Also, tighten simulation tolerances to the point where the change in accuracy of the simulation results are negligible.

Simulation tools may also offer proprietary advanced algorithms to help reduce simulation time. Although sometimes advertised as accurate, high performance simulation options, these algorithms generally reduce simulation time by simplifying the complexity of the netlist with a minimum resistance threshold. Similar to previous concerns over these circuit reduction techniques, advanced simulation algorithms may degrade the accuracy of the parasitic simulation model. A native SPICE simulation algorithm is recommended to preserve the accuracy of simulation results.


In summary, careful consideration of the tradeoffs between accuracy and performance can be summarized into three main criteria for the circuit verification of integrated power switches:

  1. Limit or avoid VIA reduction techniques with the parasitic extraction tool.
  2. Maintain a low (or 0 Ω ) minimum resistance threshold with parasitic extraction and simulation tools.
  3. Use a native SPICE simulation algorithm to prevent circuit reduction techniques that degrade accuracy.
  4. Utilizing these recommendations in the circuit verification of an integrated power switch can help accurately model a parasitic network with an increased degree of confidence.

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