Achieve sample synchronization among data converters

Multi-carrier communications systems based on OFDM, including 3GPP Long Term Evolution, utilize quadrature sampling and rely on the preservation of precise signal phase information in the transmitter and receiver. Indeed, OFDM systems must preserve phase coherency at the sample level for the digital signal processing algorithms to be valid. In the past, communication system engineers had to use proprietary synchronization techniques (typically involving shallow FIFOs and programmable logic based state machines) at the board-level to guarantee quadrature sample synchronization. The JEDEC JESD204A specification is intended to address this commonly found technical requirement, and foster interoperability among data converters and commonly used logic devices such as FPGAs.

LTE Downlink Air Interface Basics

The 3GPP Long Term Evolution (LTE) air interface is called High Speed OFDM Packet Access (HSOPA). This standard defines a downlink (i.e., base station to handset) physical layer based on Orthogonal Frequency Division Modulation (OFDM), with QPSK (Quadrature Phase-Shift Keying), 16-QAM or 64-QAM (Quadrature Amplitude Modulation) used for the downlink PHY.

OFDM QAM uses multiple subcarriers, tightly-spaced in the frequency domain (15 KHz between subcarriers), to optimize spectral efficiency, among other things. LTE standard defines twelve QAM subcarriers together as a “resource block”, with 100 resource blocks occupying a 20 MHz slice of spectrum.

In the LTE downlink protocol, the radio frame is 10 ms long, comprising 10 sub-frames of 1 msec each. Every sub-frame consists of 2 slots where each slot is 0.5 ms (or 2000 slots/sec). 64-QAM encodes 6 bits per symbol, and LTE fits seven symbols in each slot. When utilizing 20 MHz of transmission spectrum, the theoretical maximum downlink bandwidth is approximately 100 Mbits/sec. [100 resource blocks/20 MHz of spectrum ∗ 12 64-QAM subcarriers / resource block ∗ 6 bits / subcarrier symbol ∗ 2000 slots /sec ∗ 7 symbols / slot = 100.8 Mbits/sec per 20 MHz of transmission spectrum].

In OFDM QAM, adjacent subcarriers are orthogonal, or 90 degrees phase shifted, enabling this tight frequency division multiplexing with minimal interference between channels. In a conventional LTE base station OFDM downlink transmitter, a DSP or FPGA outputs two digital streams: an “in-phase” I channel and a “quadrature” Q channel, phase-shifted by 90 degrees. These digital signals are typically converted into analog signals by a high-speed dual-channel DAC, modulated (i.e., frequency multiplication “up conversion”) to the RF carrier frequency, then summed. This signal is then sent to the RF amplifiers for tower transmission.

In order for the OFDM system to function properly, the analog signal reconstruction step in the transmitter signal chain must preserve the phase modulation fundamental to orthogonal frequency division multiplexing (i.e., quadrature amplitude modulation, which is the amplitude modulation of two signals precisely 90 degrees phase shifted). This means the I channel DAC and the Q channel DAC must be perfectly synchronous at the sampling rate level.

The new JEDEC JESD204A data converter interface standard provides a mechanism for sample rate accurate synchronization between DAC channels. JESD204A uses 8B/10B encoding, and dedicated in-band control symbols enabled by 8B/10B encoding to establish and maintain precise sample rate synchronicity between converter channels.

For the purpose of setting context, JEDEC JESD204A is a new interface standard for data converters. Conventional high-speed data converters typically use parallel and serial LVDS interfaces. By contrast, JESD204A is a high-speed serial interface, up to 3.125 Gbits/sec, defining point-to-point, differential signaling lanes, using CML-compatible electrical switching levels. The standard specifies a bit error rate of 10-12, and if an implementation complies with the jitter specification eye diagrams and other JESD204A electrical specifications, the distance between the JESD204A transmitter to the JESD204A receiver can extend to 20 cm without bit errors. The primary merit of this new interface standard is pin count reduction on the data converter (ADC and/or DAC) and processor or FPGA, which not only reduces the integrated circuit cost structure, but also makes the PCB cost lower and the PCB layout easier. It is akin to the change from parallel ATA to serial ATA. It is common knowledge that serial interfaces are becoming increasingly prevalent in computer and communication system applications.

8B/10B Coding – Brief Introduction

It is necessary to delve into 8B/10B coding briefly to describe the control symbol mechanism used to establish and maintain channel sample coherence in the JESD204A standard. The 8B/10B scheme uses 10 bits (capable of encoding 1024 bit patterns) to encode bytes (256 bit patterns). JESD204A, like many other high-speed serial standards, assigns two bit patterns for each user data symbol. The two patterns are binary inverses, such as 001111 0100 and 110000 1011, which are selected dynamically according to a computed “running parity”, to enable digital signal transmission with long-term zero direct current on the differential pair. Zero dc transmission, which is managed by a running parity embedded state machine in the transmitter circuit, has several merits, such as the ability to ac couple the signal, and the ability to detect single bit errors. Thus 512 of the 1024 bit patterns encodable with 10 bits are consumed with the 256 non-inverse and 256 inverse bit patterns. The 8B/10B scheme throws away some of the remaining patterns; for example, patterns which have strings of six or more consecutive 1s or 0s (such as 01111 11000 or 11000 00011) are excluded, as are patterns in which the number of zeros and the number of ones differ by four or more (such as 11000 10000 or 11110 11100), as these tend to disturb the desired zero dc or zero bias. With all such exemptions included, 8B/10B still has numerous bit patterns available not needed for user data symbols. JESD204A uses several of these unused patterns as in-band control symbols. In the JESD204A standard, these control symbols (note there are non-inverse and inverse bit pattern versions of each control symbol) are designated “R”, “A”, “Q”, “K”, “F”, etc.

There are three synchronization protocols in JEDEC JESD204A, which relate to maintaining channel coherency for 4G air interfaces such as LTE. The first of these is called “code group” user data synchronization. JESD04A includes a hardware signal called SYNC~, sent from the receiver (DAC) to the transmitter (FPGA). At system reset (or subsequently, should user data synchronization be lost), the receivers assert SYNC~, causing multiple “K” control symbols to be sent from the transmitters. Once four valid K control symbols are received, the receiver de-asserts the SYNC~ signal. The transmitter then sends valid 10B user data symbols at the beginning of the next frame, and the transmitter (FPGA) and receiver (DAC) subsystem is now sample synchronized.

The second synchronization protocol is lane (or channel) alignment. In typical base station downlink systems, the I channel and the Q channel are carried on two adjacent lanes of a dual channel high-speed DAC. In JESD204A, the lane alignment protocol occurs immediately after the code group user data synchronization protocol described above. In this protocol sequence, the “R” control symbol signals the receiver that lane alignment is underway. The “A” control symbol marks the end of the lane alignment protocol sequence, and the subsystem is now channel synchronized.

The third synchronization protocol is the frame alignment monitoring protocol. Note that JESD204A uses a hardware frame clock signal, a multiple or sub-multiple of which is also generally used as the data converter sample clock, the absolute timing reference for the transmitter / receiver data acquisition system, and which must exhibit low jitter. In this maintenance protocol, 8B/10B user data symbols are themselves used as periodic frame alignment symbols (a technique known as character replacement), enabling frame alignment without data loss. There are two modes of this protocol, both of which use the “F” and the “A” control symbols.

In the case when optional data scrambling is disabled, the transmitter examines the last data byte in the current frame, and if it equals the last data byte in the previous frame, the transmitter replaces that byte with an F frame alignment control symbol. Upon detecting an F control symbol, the receiver replaces it with the value of the byte decoded at the end of the previous frame.

In the case when optional data scrambling is enabled, the transmitter examines the last byte in the current frame, and if it equals 0xFC, the transmitter replaces that byte with an F frame alignment control symbol. If the last byte in the current frame equals 0x7C, the transmitter replaces that byte with an A frame alignment control symbol. Upon detecting an F or A control symbol, the receiver replaces it with 0xFC or 0x7C, respectively. The JESD204A data scrambler naturally generates a frame alignment control symbol on average once every 256 frames.

In both cases (with scrambling disabled and with scrambling enabled), if the receiver detects two successive valid frame alignment control symbols (F or A) in the same position, but not at the end of their associated frames, the receiver re-aligns its frame to the position indicated by the frame alignment control symbols. Note that this periodic frame alignment monitoring protocol is optional, because certain conversion signals (such as noise-free periodic signals possessing a harmonic relationship to the sample clock frequency) may not generate frame alignment control symbols when scrambling is disabled; generally this problem can be overcome with a small amount of dither.

Designers/implementers should refer to the JEDEC JESD204A specification for complete details on these synchronization and alignment protocols.

There are alternatives to JESD204A for data converter channel synchronicity, but they are proprietary and relatively complex. For example, programmable logic is typically used to synchronize the RESET signal issued to the data converters. Additionally, shallow FIFOs are used to buffer the DAC input samples, with the FIFO outputs typically clocked synchronously, to ensure that the I and Q channel samples arrive at the DACs at precisely the same time (within the clock skew budget). These shallow FIFOs can be implemented in programmable logic (FPGA) as well. Note that for 14-bit parallel input data converters, these FIFOs consume relatively little in terms of logic gates, but quite a lot of I/O pins, which are relatively expensive on FPGA devices. The use of JESD204A data converters eliminates this logic complexity and I/O expense.

LTE MIMO and JESD204A – A Perfect Fit

The 3GPP LTE standard also supports MIMO (Multiple Input Multiple Output) spatial multiplexing / antenna diversity, both single user (SU-MIMO) and multi-user (MU-MIMO). The most common LTE MIMO system implementation is the so-called “2 by 2” configuration (two receive antennas and two transmit antennas), which provides 172.8 Mbits/sec of peak downlink bandwidth in 20 MHz of spectrum. This means that the receiver requires four ADC channels (two I channels plus two Q channels) and the transmitter requires four DAC channels (two I channels plus two Q channels). The JESD204A standard comprehends the requirements for the quad-channel ADCs and DACs needed for the dual receivers and dual transmitters in a 2 by 2 LTE MIMO configuration. Specifically, the three synchronization protocols described above (code group, lane alignment and frame alignment monitoring) all extend in a straightforward fashion to support four channel JESD204A data converters. Indeed, these protocols also extend to support the eight channels of high-speed data conversion required to support “4 x 4” LTE MIMO configurations. 4 x 4 LTE MIMO provides 326.4 Mbits/sec of peak downlink bandwidth in 20 MHz of spectrum.


The new JEDEC JESD204A high-speed data converter interface is well suited to the emerging 4G LTE system architecture. This new serial digital interface eliminates proprietary and costly external synchronization circuitry required by OFDMA QAM through the use of in-band synchronization control symbols made possible by the use of the 8B/10B coding scheme. JESD204A also minimizes FPGA and data converter I/O count (package cost) and supports 2 x 2 and 4 x 4 LTE MIMO without any additional specification changes or hardware costs. Based on these merits, JEDEC JESD204A high-speed data converters look to be an excellent choice for LTE radio subsystem design engineers.

Author Profile: Maury Wood is marketing manager for high-speed data converters at NXP Semiconductors (Caen, France)

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