In my haste to get “A Fast-Settling Bias Voltage Filter with High Ripple Rejection” out there, I forgot to cover an important aspect, that on the face of it might look to be a showstopper. It turns out that it’s not so big a deal, but does demonstrate something quite interesting about that class of filter design.
To recap, in that article I presented a ‘DC-free’ filter that not only effectively suppressed ripple on a very high voltage bias line, but also settled very quickly following changes in that voltage. We also proudly showed the settling behavior of a couple of variants of that filter topology to a step change in the input voltage. The particular step I was studying was a unit step, i.e. a 1-V change in input voltage.
However, I also implied a rapid settling time to the much-larger input step that results when the actual 180 V bias voltage we were filtering was turned fully on and off. Our simulations predict a negative spike of 600 V at the output of each op amp when the input voltage steps up from zero to 180 V. A same-size, positive-going spike follows when the input voltage steps back down to zero again.
To read the entire article about what was really going on, click here.
(This article originally appeared in EE Times Europe—Analog .)
About the author
Kendall Castor-Perry is a Principal Architect at Cypress Semiconductor Corp., doing mixed-signal system analysis and design for the new PSoC platform. Kendall uses decades of experience in analog engineering, filtering and signal processing to capture signals across many domains, extract the information from them and do something useful with it.