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ADC Basics, Part 10B: 16-Bit Converter Gives a Gainable 12-Bit System

In part A, we looked and several ways to implement system gain changes, finishing with a digital technique based on shifting bits to the right. Now, we continue with…

Noise
Noise generators in this circuit are the PGA and ADC driver op amp. The noise generated by the 16-bit SAR-ADC exists in the converter’s last two bits. In our gain algorithm, we use only bits 3 through 16.

In terms of noise, the only component that changes is the PGA. The noise contribution from this device changes with gain. The ADC-driver-op-amp noise is consistent across all gain changes, at 13μVRMS (OPANOISE ).

The PGA referred-to-input noise (RTI) is 12μV rms. At a gain of 1 V/V, the PGA noise is:

Although the PGA’s internal amplifier has a voltage feedback topology, the frequency/gain response does not follow the expected response. This is because the internal compensation capacitor is changed at the same time that the gain resistor is changed. This internal compensation capacitor determines the lowest frequency pole of the amplifier’s open-loop gain curve. This change in the compensation capacitor changes the frequency response as well as the device’s slew rate and settling time. In Table 1 you can see the bandwidth of the PGA with various gain settings.

Table 1

Noise performance over PGA/ADC gain options: RTI = referred to input, RTO = referred to output.

Noise performance over PGA/ADC gain options: RTI = referred to input, RTO = referred to output.

Table 1 shows the system noise from the circuit in Figure 1 (from part A) with a system gain of 16 V/V.

The noise at a system gain of 128 is just over half the LSB (0.529) of a 12-bit, 5 V system.

System timing
The performance specifications of PGA and SAR-ADC can be utilized to an advantage in any application circuit. However, the limiting specification between these two devices is the ADC’s clock rate. As we have seen before, the system conversion speed is further reduced by the settling time of the PGA amplifier.

In Figure 3, the clock rate of the ADS8326 lowers the maximum PGA116 clock to 6 MHz. Additionally, this ADS requires 24 clocks to perform a conversion as compared to the 16 clocks for the PGA. After the PGA changes channels, the analog output settles. The times controlling the settling time of the PGA are the channel/gain select time of 0.4 ms, and the settling time of 2.6 ms (G = 16). A guard band of 30 percent is added to these times to accommodate the op amp production process, where internal components can vary. Using the guard band on the times listed above, 4.0 ms is allotted for the PGA to settle. The total system conversion time for the PGA/ADC combination is 10.7 ms or 94 ksps.

Figure 3

Clocking, system throughput, clock = 6 MHz.

Clocking, system throughput, clock = 6 MHz.

Conclusion
The accuracy of this system is good for 12-bit operation up to PGA gains of 128 V/V. Referring to Table 2, there is little difference with the DC specifications between this article and Parts 8 and 9 of this series. Although this system is slower, the noise levels from this system are significantly lower than the noise in the previous two systems.

Table 2

System specifications for: (A) Figure 1 circuit from this article, (B) system specifications for Figure 1 circuit from ADC Basics Part 8, and (C) system specifications for Figure 1 circuit from ADC Basics Part 9.

System specifications for: (A) Figure 1 circuit from this article, (B) system specifications for Figure 1 circuit from ADC Basics Part 8, and (C) system specifications for Figure 1 circuit from ADC Basics Part 9.

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