ADC Basics, Part 11A: Take the 24-Bit Leap

As we looked for a 12-bit system to handle data loggers, handheld meters, automotive systems, or monitoring systems, we used 12-bit analog-to-digital converters (ADCs), and even a 16-bit ADC, to solve our problem. Again, the system we are designing today must produce 4,096 possible digital outputs to a microcontroller or processor. What if we just jump away from the ADC-SAR converter and really use the unorthodox approach that was utilized in ADC Basics, Part 10B: 16-Bit Converter Gives a Gainable 12-Bit System? A 24-bit Δ-Σ ADC is an excellent place to start.

In ADC Basics, Part 8: A 4-System Matrix With PGA + 12-bit SAR, we used a programmable gain amplifier followed by a 12-bit SAR ADC. In our second system, ADC Basics, Part 9: PGA Embedded in an 8-Channel, 12-Bit SAR, an eight-channel, 12-bit SAR-ADC allowed the inclusion of an analog function between the multiplexer and ADC. With our third system, ADC Basics, Part 10A: 16-Bit Converter Gives a Gainable 12-Bit System, we jumped into using a 16-bit SAR ADC, where this converter handled most of the signal gain through process gain. This third system provided a dramatic improvement in system noise, at the expense of a reduced throughput time.

Leap to a 24-bit Δ-Σ converter
So here we go — we are figuratively going to throw away the bath water. I'm referring to the external programmable gain amplifier (PGA) and operational amplifier (op-amp), hoping to keep just the baby. To achieve excellent 12-bit specifications, consider a 16-channel (multiplexed), 24-bit Δ-Σ ADC (Figure 1). This device provides zero-cycle latency with an auto-scan rate of 23.7ksps.

The input multiplexer of this device accepts combinations of eight differential or 16 single-ended inputs. The full-scale differential range is 5 V, or a true bipolar range is ±2.5 V, while operating with a 5V reference. In this device, a fifth-order sinc ([(sin x) / x]) digital filter follows the fourth-order Δ-Σ input modulator.

Figure 1

A 24-bit Δ-Σ ADC with a 16-channel multiplexer input.

A 24-bit Δ-Σ ADC with a 16-channel multiplexer input.

Digital or process gain?
The previous systems that we designed had analog/digital gains increasing by a factor of two from 1 to 128 V/V. In this system, we are going to use the process gain technique exclusively. This system process gain maxes out at 128. Figure 2 shows this how function works.

Figure 2

Process gain concept for a 24-bit Δ-Σ ADC with 19.5 effective number of bits (ENOB).

Process gain concept for a 24-bit Δ-Σ ADC with 19.5 effective number of bits (ENOB).

With the 24-bit Δ-Σ ADC, you receive a 24-bit word at the converter's serial digital output pin. You can increase the process gain by a factor of two by shifting the most significant bit (MSB) position to the right in your digital controller or processor. The number of process gains that have 12-bit words available at the output of this 24-bit Δ-Σ ADC is eight.

With this device, the noise is dramatically less than half the least significant bit (LSB) of our required 12-bit system. The device in Figure 1 has a noise level of 7.2 bits (p-p), or 4.5 bits rms (noisy bits). Because of this noise performance level, bits 24 (MSB) through 6 (MSB − 18) are completely usable in this application. As you use all of these 12-bit configurations by implementing your process gain, the referred-to-input (RTI) noise across all process gains (1 to 128) is lower than our 12-bit system requirements. In fact, the process gain of 128 is the only gain configuration that shows any noise of 12μV-rms.

An analog low-pass filter helps you achieve this level of performance. You install this filter by using the MUX OUT and ADC IN pins (Figure 3).

Figure 3

Passive low-pass filter configuration for the ADS1258, 24-bit, Δ-Σ ADC.

Passive low-pass filter configuration for the ADS1258, 24-bit, Δ-Σ ADC.

In the second part of this two-part blog, we will calculate filter component values, take a closer look at Δ-Σ performance, and summarize performance of these system variations.

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4 comments on “ADC Basics, Part 11A: Take the 24-Bit Leap

  1. jkvasan
    December 25, 2013


    I have always wondered how these 24 bit devices work. Though we are all aware of sigma delta operations and basic theory of such devices, it is interesting to know the intiricate details.

  2. Bonnie Baker
    December 26, 2013


    Thanks for talking a look at this article. The basic theory of the Delta-sigma is important to know and understand, but the most important topic where these converters are concerned it how to use the characteristics of this converter to your advantage. This article addresses the the usage of process gain and how that impacts the noise in your circuit. In terms of noise, the converter's noise only impacts you when you use the lower bits. If you are looking for a 12-bit word the 24-bit converter gives you a lot of flexibility.

  3. Victor Lorenzo
    December 27, 2013

    Bonnie, thanks for writing this article series.

    Does “If you are looking for a 12-bit word the 24-bit converter gives you a lot of flexibility ” mean that for achieving a given resolution with Delta-Signma converters it is necessary to use higher resolution converter and discard one or more LSBs?

  4. Bonnie Baker
    December 27, 2013

    Victor, you are welcome. Thanks for spending time with this article.

    If you do the math with your 24 bit converter, you will find that you have 2( DSbits – SARbits) or ideally 4096 12-bit converters in converter. This is done by utilizing the process gain function that I mentioned. For the converter in this article, the effective number of bits is ~19+ bits. In this scenario, there are 128 12-bit converters in the converter. Now this is done with a straight forward Delta-sigma converter. You can see that if your converter has a front end PGA function this concept has legs!

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