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ADC Basics, Part 11B: Take the 24-Bit Leap

In the first part of this blog, we considered the 12-bit SAR ADC as part of a DAS. We then started looking at a 24-bit Δ-Σ ADC to see if it could provide the level of performance needed. We had started considering the issue of noise and how to filter it.

In this circuit, place the analog anti-aliasing or low-pass filter between the multiplexer and the converter's input. Use equation 1 for this low-pass filter:

Where ER = ADC's effective resolution
k = 1.38•10−23 JK−1 (Boltzmann's constant)
T = temperature in degrees Kelvin
FD = frequency of ADC output data rate

To calculate CFLT :

CFLT = 1/(2πRFLT •FD )

The filter section from Figure 3 of part A of this blog can be seen to the right. It has a differential input and output. Notice that there are two separate but equal resistors. The filter capacitor helps to filter noise as it manages charge-dumping from the input Δ-Σ converter's sampling structure.

System timing
Figure 1 shows the internal, intermediate conversions of the Δ-Σ converter with a fifth-order digital filter. Notice the hidden conversions , which are an artifact of the order of the digital filter in the Δ-Σ converter. With the ADS1258, you can configure the converter so that the user never sees these hidden conversions.

Figure 1

The internal conversion algorithm for the Δ-Σ ADC, based on the ADS1258.

The internal conversion algorithm for the Δ-Σ ADC, based on the ADS1258.

If the conversion algorithm described in Figure 1 is used, the device exhibits zero-cycle latency ADC. In other words, all of the output data from this converter is fully settled. An ADC with zero-cycle latency also can be described as having single-cycle settling, or single-cycle conversion.

In the zero-latency, auto-scan configuration, the throughput time for the Δ-Σ converter is 42.2μs or 23.7 ksps.

The accuracy of this system is good for 12-bit operation all the way up to a gain of 128. Referring to Table 1, you can see where this configuration finally gives the user true rail-to-rail input performance. Again, this system is slower, but the noise levels are significantly lower than the noise in the previous three systems.

Table 1

Gain of 16 system specifications: A) Figure 1 circuit from this article. B) system specification for Figure 1 circuit from ADC Basics, Part 10. C) system specifications for Figure 1 circuit from ADC Basics, Part 9. D) system specifications for Figure 1 circuit from ADC Basics, Part 8.

Gain of 16 system specifications: A) Figure 1 circuit from this article. B) system specification for Figure 1 circuit from ADC Basics, Part 10. C) system specifications for Figure 1 circuit from ADC Basics, Part 9. D) system specifications for Figure 1 circuit from ADC Basics, Part 8.

Like the ADS7951, the ADS1258 provides features beyond a standalone ADC. The chopper input on these devices helps to provide a device with better offset voltage at room temperature and over the full specified temperature range of the device. Beyond the ADC function, the ADS1258 has a sensor bias current source, an eight-channel GPIO, and various system diagnostic options.

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